Final Activity Report Summary - LFAPDIFI (Digital adaptive filter design based on the fast affine projection algorithm and the logarithmic number system arithmetic)
Digital adaptive filters are an important aspect of Digital Signal Processing (DSP) and are used in a wide variety of data communication systems for echo and noise cancellation amongst other tasks. Filters are vital in these systems for improving the quality of received signals. Recently the demand for versions of filters that deliver improved performance and stability has grown. Critical to the performance of these filters is the algorithms ability to adapt to the noise characteristics of a signal. The current standard algorithms are easily implemented; however they take a significant length of time to adapt to the noise characteristics of a signal and struggle to track changes in the noise characteristics once they are running. A new class of adaptive algorithms has emerged which has substantially better performance in this regard, without requiring large amounts of additional computing resources. These algorithms are called Fast Affine Projection (FAP) algorithms.
Meanwhile the use of reconfigurable computer processors such as field programmable gate arrays (FPGAs) has seen dramatic growth in recent years. Many of these FPGAs are used for performing Digital Signal Processing (DSP), to the point that certain FPGA vendors now sell FPGAs customised to the needs of DSP systems. However, the use of FPGAs for digital adaptive filters is an area where much work is still to be done.
We have implemented and evaluated one of these algorithms for FPGAs using the innovative Logarithmic Arithmetic system.This system provides excellent performance for FPGA based DSP systems and due to its resource efficient nature allows us to use substantially smaller and cheaper FPGAs than would be possible with other arithmetic systems. Our implementation is stable and has excellent filtering properties which we have demonstrated by filtering noise from real speech signals.
Our implementation is a significant breakthrough in the design and implementation of digital adaptive filters in FPGA devices and provides the first available hardware implementation of a new generation of adaptive digital filters with superior adaptability and tracking ability to any existing implementation.
Meanwhile the use of reconfigurable computer processors such as field programmable gate arrays (FPGAs) has seen dramatic growth in recent years. Many of these FPGAs are used for performing Digital Signal Processing (DSP), to the point that certain FPGA vendors now sell FPGAs customised to the needs of DSP systems. However, the use of FPGAs for digital adaptive filters is an area where much work is still to be done.
We have implemented and evaluated one of these algorithms for FPGAs using the innovative Logarithmic Arithmetic system.This system provides excellent performance for FPGA based DSP systems and due to its resource efficient nature allows us to use substantially smaller and cheaper FPGAs than would be possible with other arithmetic systems. Our implementation is stable and has excellent filtering properties which we have demonstrated by filtering noise from real speech signals.
Our implementation is a significant breakthrough in the design and implementation of digital adaptive filters in FPGA devices and provides the first available hardware implementation of a new generation of adaptive digital filters with superior adaptability and tracking ability to any existing implementation.