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Content archived on 2024-04-16

High-Performance Sub-Micron SOI/CMOS Technologies

Objective

The SUBSOITEC project aimed to develop high-performance SOI (Silicon On Insulator)/CMOS technologies for future VLSI circuits, which, while competitive with standard bulk CMOS processes, are compatible with them and offer the inherent advantages of SOI technologies.
The SUBSOITEC project aimed to develop high-performance silicon on insulator (SOI) complementary metal oxide semiconductor (CMOS) technologies for future very large scale integration (VLSI) circuits, which, while competitive with standard bulk CMOS processes, are compatible with them and offer the inherent advantages of SOI technologies. The project evaluated a complete SOI/CMOS process with 0.7 micron design rules. The programme included development work on silicon implanted oxide (SIMOX) SOI substrates, on the 0.7 micron SOI technology, on device and physics modelling, on design, and on the test and characterization of complex VLSI demonstrators. The work performed in the area of materials fabrication and device evaluation yielded excellent results that compare favourably to work done outside this project. The SOI substrates are among the best available world wide, even for substrates with very thin top silicon thicknesses. The compatibility of SOI processes with standard bulk CMOS technology was considered as a major goal. The portability of bulk design to SOI was studied and implemented. The main difficulties (such as electrostatic discharge (ESD) protection devices and the absence of substrate contacts) are now solved. The ability to realize complex VLSI circuits on SOI with 0.7 micron design rules will be demonstrated, and evaluation of the industrial aspect will be achieved in a comparison of a design in a CMOS SOI with a CMOS bulk process with the same design rules, and by several SOI demonstrators including a 64 k static random access memory (SRAM) and 2 custom chips.
CMOS circuits with deep sub-micron geometries require very complex and expensive processes on bulk silicon. An acceptable challenger to bulk Si is SOI material which allows, in principle, a significant reduction of the number of process steps leading to an enhancement of the yield of complex VLSI chips and a reduction in cost. Two other advantages of CMOS on SOI are the reduction of parasitic capacitance (which increases circuit speed), and immunity towards radiation and heavy ion effects (needed for space applications), making this technology competitive with bulk BICMOS technology.

Topic(s)

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Call for proposal

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Funding Scheme

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Coordinator

THOMSON CSF SEMICONDUCTEURS SPECIFIQUES
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3300 RUE JEAN-PIERRE TIMBAUD
92402 Courbevoie
France

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Participants (9)