The QUICKCHIPS project aimed to develop a low-cost quick prototyping and small-volume production system of ASICs (gate array and sea-of-gates) using a DWL 2.0 (Direct Write Laser) machine for wafer personalisation. Activities included the development of a DWL 2.0 machine for Very Quick Turnaround Line (VQTL) ASIC fabrication, the development of a foundry-independent design system (the Uncommitted Design System), and the thorough evaluation of the usability of project results for small and medium-sized enterprises (SMEs).
The QUICKCHIPS project aims to develop a low cost quick prototyping and small volume production system of (ASIC) (gate array and sea of gates) using a direct write laser (DWL) 2.0 machine for wafer personalisation. Activities include the development of a DWL 2.0 machine for very quick turnaround line (VQTL) ASIC fabrication, the development of a foundry independent design system (the uncommitted design system) and the thorough evaluation of the usability of project results for small and medium sized enterprises SME).
The first prototype of the DWL 2.0 machine was displayed at SEMICON Europe '91, and preproduction models were then constructed for beta site testing. The evaluation identified corrections needed for the equipment toperform at the target geometries and its feasibility was confirmed.
Studied, including all facets of the infrastructure needed to provide very quick turnaround ASICs, were completed with specifications for implementation. This work included optimum telecommunication methods, design frameworks, process technologies for multilayer interconnects, process equipment requirements including integration concepts and an application review for the requirements of fast turnaround ASICs in Europe.
A first tentative demonstrator design was achieved using tools which are being adapted to an open design environment. Contacts with silicon foundries have been established.
The DWL 2.0 machine, under development by one of the partners, exploits direct write laser-based lithography techniques to achieve multi-layer personalisation on a generic blank array, allowing the use of multivendor gate array and sea-of-gates wafers. Rapid image-recognition methods are used for laser beam guidance, which scans by means of acousto-optic deflectors and modulators. A multi-layer process will later be developed in the project, as well as automated wafer handling, process automation and process clustering and integration.
The Uncommitted Design System will provide the user with a wide choice of design techniques and tools by the adoption of a design framework for CAD tool integration. It will provide foundry independence by means of uncommitted libraries, allowing for part of the design cycle of a circuit to be performed without an initial commitment to a particular vendor or chip. This flexibility will allow the automatic generation of multiple silicon implementations for the same design. A geographical network of non-homogeneous platforms will be tested out, that allow remote access to design tools and libraries.
A detailed analysis will examine conditions which characterise an operation targeted at SMEs that could be realised using the projects results, facilitating SME access to the most advanced technologies.