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Robust mixed-signal design methodologies for smart power ICs


Smart power circuits and technologies contribute in a unique way to the realization of the system-on-chip concept by combining digital logic with analogue signal processing and power and high voltage switching. The main objective of this project is to enable a robust design of smart power circuits leading to a first-time-right design with built-in reliability and thus avoiding very costly over-dimensioning. To achieve this ambitious goal, compact models will be built that accurately describe power device operation including extensions to verify safe-operating area conditions. The devices to be modelled include the lateral DMOS, vertical DMOS and LIGBT fabricated in bulk silicon and power devices realized in advanced SOI technology. Model extensions are planned for device ageing due to hot-carrier injection, statistics due process variations, device matching and layout effects such as large area closed-cell matrices.

An important feature will be an accurate description of the internal device temperature plus a coupling to package thermal models and EMC modelling. The final goal is to achieve a system level design flow for smart-power SoC using complex transistor level simulations or generated black-box models. Full smart power circuits will be simulated with the new design flow and models will be assessed and calibrated against experimental measurements. The gain in performance and robustness will be quantified.

The project therefore aims at providing the EC "power" industrial community with new, highly robust tools to design and characterize smart power devices and circuits. This will strengthen and significantly advance ECs position as a fast growing, world supplier of smart power technologies. Design and fabrication of highly reliable and efficient Smart Power circuits is one of the most important strategic ways to reduce drastically energy losses in power systems by ensuring optimal energy conversion at all times.


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Participants (8)