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Content archived on 2024-06-18

Novel scalable memory concepts and technologies


With the scaling of successive generations of CMOS technologies, further scaling of the different memory types (DRAM, Flash, FeRAM, MRAM) is no longer feasible due to physical and/or cost limitations. Furthermore, the processes for various types of memories on CMOS are increasing in complexity and as a result becoming mutually exclusive. This threatens the further scaling of systems-on-chip, on which several memory types (SRAM, DRAM, Flash, ...) often must be integrated simultaneously.

As a result, there is a very strong driving force to develop novel memory concepts worldwide. The purpose is to find materials and concepts that re-unite the following 5 major characteristics:
(1) scalable for at least several generations from the 45nm CMOS node on;
(2) non-volatile;
(3) fast (ns and less) intrinsic switching mechanism;
(4) the technology and materials must be compatible with present-day and future generations of CMOS;
(5) a single and simple technological platform to produce a single unified memory cell should allow to generate memories with various characteristics by variation of the memory architecture in which such cell is embedded.

The present consortium groups two European semiconductor manufacturers, who have, for different applications, performed several years of research to screen and pre-select candidate memory cells and materials. This strong background allows the consortium to focus on a limited number of two most promising options: one organic charge transfer material cell, and one ferro-electric Schottky barrier memory cell.

The purpose of the research is to assess the performance and validate the possibility to implement cross-point memory cells based on these two options in standard backend-of-line CMOS processes and to demonstrate a reliable and scalable new memory cell concept with cell size down to 4 F¿, where F is half the minimum metal pitch.

Call for proposal

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Participants (4)