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Joint Logic Project

Objective

The objective of the Joint Logic Project was to develop the powerful CMOS processes required to improve the capability of European electronic product manufacturers to offer competitive products on a timely basis.
The major objective of project 5080 was the demonstration of the capability of a 0.7 micron logic complementary metal oxide semiconductor (CMOS) technology. This was done according to plan. Demonstrators have been made in most cases incorporating a common 0.7 micron test module and qualification of 0.7 micron technology is in progress.

Both Philips and Siemens produced first silicon of their 3 layer metal demonstrator with excellent performances.

Test procedures for test chips and demonstrators are implemented and a scribe line test insert was designed and distributed as (GDSII) tape among the partners.

Commonality on characterisation procedures, reliability procedures and parameter definition was assessed and new common procedures on reliability measurements of dialectrics and metallisation patterns were created. A complete synthesis on device optimization was generated.

Several processing techniques and process problem areas were evaluated, compared and optimised or improved.

Major improvements were encountered in the multilevel metallisation processes and the isolation methodology.

Qualification of the 1.0 micron analogue process was realised. Several process improvements have been introduced and matching performance and linearity of analogue components were intensively characterised. A process flow for a 0.7 micron analogue process was defined.

The various process architectures for 0.5 micron digital CMOS were compared and a first draft set of design rules generated.

A common demonstrator of a multichip module in a low cost quad flat package was developed.

2 types of demonstrators were assembled: one with fully gold wire bonding, and the other with partially aluminium wire bonding (inner connections).
The Joint Logic Project is part of the seven-year JESSI technology programme ("Green Book"). The project is subdivided into a number of phases, as shown below.

Period 6/90-12/91, Phase JLP-1, Objective 0.7 micron CMOS logic, Project no. 5080, 1.0 micron options

Period 1992-94, Phase JLP-2, Objective 0.5 micron CMOS logic, Project no. 7363, 0.7 micron options

Period 1995-96, Phase JLP-3, Objective 0.35 micron CMOS logic, 0.5 micron options

The objective in the first phase was the demonstration, by each company, of the capability of a 0.7 micron basic logic process, and all subprojects contributed to solve technical problems associated with this objective. Each company provided a company-specific demonstrator in order to verify the competitiveness of the process for specific applications.

A second objective was to produce and measure first silicon for various functional options, such as low-power non-volatile memories in 1.0 micron technology, and analogue logic in 1.0 and 0.7 micron technologies.

In addition, these CMOS processes (basic and options) may serve as an input for high performance BICMOS processes, in which high-performance bipolar is combined with sub-micron CMOS.

A third objective was the generation of a first set of target design rules for a 0.5 micron core logic technology.

Coordinator

PHILIPS INTERNATIONAL BV
Address
Gerstweg, 2
6534 AE Nijmegen
Netherlands

Participants (9)

EUROPEAN SILICON STRUCTURES S.A.
France
Address
Zone Industrielle
13106 Rousset
GEC Plessey Semiconductors plc
United Kingdom
Address
Caswell
NN12 8EQ Towcester
MATRA-MHS
France
Address
3008 Route De Gachet
44087 Nantes
MIETEC
Belgium
Address
Westerring, 15
9700 Oudenaarde
SGS THOMSON MICROELECTRONICS SA
France
Address
7 Avenue Gallieni
92253 Gentilly
SIEMENS AG
Germany
Address
Wittelsbacherplatz
80333 Muenchen
STC plc
United Kingdom
Address
1B Portland Place
W1N 3AA London
Telefunken Microelectronic GmbH
Germany
Address
Theresienstraße 2
74072 Heilbronn
Thomson Microelectronics Srl SGS
Italy
Address
Via Carlo Olivetti 2
20041 Milano