The increasing demand for size reduction in ferroelectric devices is faced with both technical and fundamental problems at the nanoscale level. Among the technical challenges, one of the main areas of research is, as ever, how to store more charge per unit ar ea in a cost and time-effective manner. Regular arrays of ferroelectric nanotubes offer an interesting possibility in this respect, as a high storage density can be achieved through a high aspect ratio of the nanotube-based cylindric capacitors. In addition, such nanotubes also have potential uses in the field of microelectronic actuators (MEMS).
However, due to the technical difficulty in applying electrodes and making electrical contacts in such structures, the functional properties of the nanotubes have not y et been tested. This will be one of the priorities of the present project. On the other hand, planar-like geometries are easier to manufacture, which is why they are usually the preferred shape for both fundamental research and industrial applications. Even t hen, patterning of regular arrays at the nanoscale level is not trivial. In this respect, an appealing alternative to the usual lithography method is the idea of self-patterning of ferroelectric nanostructures. We will explore this by the use of some ideas borrowed from the field of semiconductor quantum dots.
Finally, any project concerned with miniaturisation in ferroelectrics must face the fundamental problem of the "si/e effect", i.e., the decreasing of the dielectric constant of ferroelectric thin films with respect to their bulk counterparts. One of the causes of this seems to be the accumulation of space charge at the interface between electrode and dielectric. In order to minimise this charge it is necessary to know in detail the band structure of the metal and the dielectric. Such knowledge must include the energy levels corresponding to impurities and deep traps in the band gap of the ferroelectric.
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