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Submicron CMOS Technology

Objective

The objective was to develop the necessary building blocks for a 0.7micron CMOS process, primarily dedicated to the production of high-speed (within the limitations imposed by MOS) digital circuits.
In order to allow the programme to proceed with the best chances of success, two main phases were identified and organised, the first focusing on an intermediate step at the 1 micronlevel, the second on the final 0.7micron CMOS family. Two additional ta sks were added to the original project at the end of the first year, making eight tasks in all. These addressed the topics of architecture, optical and electron-beam lithography, MOS structures, isolation, interconnect, and refractory metal gates. It was the responsibility of the first task to arrange the pilotline demonstration of the 1micron and submicron demonstrators; the other tasksprovided the technology inputs for this.
The objective was to develop the necessary building blocks for a 0.7 micron complementary metal oxide semiconductor (CMOS) process, primarily dedicated to the production of high speed digital circuits.

2 main phases were identified and organised, the first focusing on an intermediate step at the 1 micron level, the second on the final 0.7 micron CMOS family.

The demonstrator of the 1 micron CMOS process was fabricated.

The demonstrator device is a multichip including:
a 4 K, 6-transistor SRAM;
a 4 K, 6-transistor SRAM;
an image processor;
modules for the extraction of electrical parameters, including the common test developed for electromigration studies.
In parallel, a 64 K, 6-transistor SRAM, whose size of 27 square millimetres prevented it from being included on the multichip, was processed in the same line, making use of the same process.

A logic circuit (70 000 transistors, 35 square millimetres, 54 MHz) has subsequently been realided in the 1 mircon process. Several technologies were also developed but were not included in the 1 micron demonstrator. This was the case for electron beam lithography.
Amongst other development technologies, 3 could be included as achievements of the first phase:
trench isolation (this technology was developed and demonstrated and found compatible with 5 V power supply);
metal gate transistor (the programme was pursued up to the processing of a 16 K SRAM memory);
2 aluminium layers (test devices gave good results down to pitches of 2.8 micron and 3.6 micron for the first and second metal respectively).

A submicron core process flow, that is, a common skeleton to which different technologies could be grafted was agreed and a common set of design rules was developed. To investigate the possible evolution toward a 0.5 micron process, special advanced rules were developed.
Functional circuits based on the developed submicron CMOS process modules were demonstrated, tested and fabricated. Large density chips (256 K SRAM; 1 Mbit erasable programmable read only memory (EPROM) plus sea of gates circuit) based on the common set of design rules were manufactured.
By the end of year three, the demonstrator of the 1 micron CMOS process had been fabricated by CNET. The process is an Nwell CMOS process, with polycide gates and two metal levels. The first metal level is formed by CVD tungsten. Isolation is based on an optimised LOCOS technique, while LDD with deposited oxide spacers was used to increase the reliability of Nchannel devices.
The demonstrator device is a multichip including:
-a 4K, 6-transistor SRAM by CNET
-a 4K, 6-transistor SRAM by IMEC
-an image processor by British Telecom (obtained from the Wafer-Scale Integration project, number 824)
-modules for the extraction of electrical parameters, including the common test developed for electromigration studies.
In parallel, a 64K, 6-transistor SRAM designed by MHS, whose size of 27mm2 prevented it from being included the multichip, was processed in the same line, making use of the same process.
The access time of the 4KSRAM from CNET was 20 ns, limited by design, while the 64KSRAM by MHS showed parts with access time lower than 15ns and a stand-by current absorption of 10uA. A logic circuit (70000transistors, 35mm2, 54MHz) has subsequent
ly been realised by CNET in the 1micron process issued by SPECTRE.
Several technologies were also developed but were not included in the 1micron demonstrator. This was the case for Ebeam lithography, which after a three-year development was dropped due to the appearance on the market of Iline steppers and Gline lenses with good submicron performances. Amongst other development technologies, three could be included as achievements of the first phase:
-Trench isolation: this technology was developed and demonstrated and found compatible with 5 V power supply. However, since comparable results could be obtained with a more conventional approach, the trench was not used in the final demonstration.
-Metal gate transistor: the programme was pursued up to the processing of a 16K SRAM memory. Nevertheless, due to the lack of availability of the equipment, the work was stopped.
-Two aluminium layers: test devices gave good results down to pitches of 2.8micron and 3.6micron for the first and second metal respectively.
Exploitation
By the end of December1987 the one-micron CMOS process results were disseminated throughout eleven companies and research laboratories located in five European countries.
Additionally, Matra Harris successfully transferred the SPECTRE CMOS technology into its fast static RAM and microprocessor fabrication lines, and selected process steps are being integrated into the fabrication process of a 1M EPROM by STM.
During year four, the partners agreed on a submicron "core" process flow, that is, a common skeleton to which different technologies could be grafted and a common set of design rules was developed. To investigate the possible evolution toward a 0.5micron process, special "advanced" rules were developed for use by the research laboratories.
During year five, the process partners demonstrated and tested functional circuits based on the developed sub-micron CMOS process modules and fabricated at each of the five locations. The industrial partners manufactured large density chips (256K SRAM; 1 Mbit EPROM plus sea-of-gates circuit) based on the common set of design rules; in this way the project culminated in the provision of a multi-sourced state-of-the-art CMOS ASIC capability for Europe.

Topic(s)

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Call for proposal

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Funding Scheme

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Coordinator

Centre National d'Études des Télécommunications (CNET)
Address
98 Chemin Du Vieux Chêne
38243 Meyland
France

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Participants (10)

AARHUS UNIVERSITET
Denmark
Address
Ny Munkegade
8000 Arhus

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British Telecom plc (BT)
United Kingdom
Address
British Telecom Laboratories Martlesham Heath
IP5 7RE Ipswich

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Bull SA
France
Address
48 Rue Jean Jaures
78340 Les-clayes-sous-bois

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Consiglio Nazionale delle Ricerche (CNR)
Italy
Address
Via De' Castagnoli 1
40126 Bologna

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IMEC VZW
Belgium
Address
Kapeldreef
3030 Heverlee

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MATRA-MHS
France
Address
3 Avenue Du Centre
78054 Saint-quentin-en-yvelines

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Telettra SpA
Italy
Address
Via Tremo 30
20059 Vimercate Milano

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Thomson Microelectronics Srl (SGS)
Italy
Address
Via Carlo Olivetti
20041 Agrate Brianza Milano

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UNIV CATHOLIQUE DE LOUVAIN
Belgium
Address
Place De L'universite
1348 Louvain-la-neuve

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United Kingdom Atomic Energy Authority (UKAEA)
United Kingdom
Address
Harwell Laboratory
OX11 0RA Didcot

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