Objetivo The drive to smaller device dimensions in ULSI CMOS fabrication places considerable demands on process stability and quality control to achieve satisfactory device reliability. For this reason, ultra-clean processing based on ultra-high vacuum cluster tools has received considerable attention in recent years. ASSIST aims to gain atomic-scale control of the surfaces and interfaces in the elemental components of silicon devices (MOS gates, Schottky barrier and Ohmic contacts), and to assess the benefits of such control for current and future fabrication technologies.A study of hydrogen atom dry cleaning of silicon surfaces in the ultra high vacuum (UHV) cluster tool has been carried out. It was found possible to remove hydrocarbon contamination from the surface at temperatures of 150 C to 350 C. The native oxide, and a thin ultraviolet/ozone oxide on the silicon surface are stable to attack by hydrogen atoms for temperatures below 700 C. A time of flight (TOF) medium energy ion scattering spectrometer (MEISS) for improved sensitivity analysis impurities on silicon has been designed and built. This equipment can be used to detect light elements by recoil scattering from a silicon surface and heavy elements by backscattering analysis. The equipment will be installed on the cluster tool to replace the existing less sensitive electrostatic MEISS system. A new technique for the examination of gate oxide dielectric strength with about 20 nm spatial resolution has been developed. The technique uses a conducting cantilever in an atomic force microscope (AFM). The AFM is scanned to measure surface topography in the usual way. During the scan the instrument is periodically stopped and a voltage is applied in increasing steps between the sample and conducting cantilever. At each voltage level a Fowler-Nordheim (FN) tunnelling current is determined. The voltage ramp-up is stopped at a preset current level, set below the dielectric breakdown value. A map of the voltage required to reach the preset FN tunnelling current serves as a spatially resolved measure of dielectric quality. In measurements of thin gate dielectric (about 10 nm thick) small regions some hundreds of nm square were found to withstand fields as high as 40 MV/cm; this is a factor of three higher than found on conventional metal oxide semiconductor (MOS) capacitor test sets fabricated on similar material. This development provides for the first time the ability to test gate oxides with a spatial resolution similar to that used to measure silicon surface roughness prior to gate oxidation. Studies of pregate oxide chemical cleaning method have lead to the reappraisal of the traditional RCA clean and the proposal of a new improved procedure. This new cleaning procedure has given evidence of improved gate oxide yield. A study of the hydrogen terminated surface produced by hydrogen fluoride last step cleaning has shown a correlation between the pH of the hydrogen fluoride clean and the resultant surface roughness deduced from the relative amount of mono, di, and tri hydride species left on the silicon surface. Preliminary measurements of silicon surface roughness using UHV scanning tunnelling microscopy (STM) correlates well with the results deduced from the hydrogen termination measurements.APPROACH AND METHODS A previous Basic Research Action, PROMPT (3109), led to the development of a UHV cluster tool for the fabrication of MOS test-sets. Through the use of this cluster tool and integrated diagnostic facilities (STM and ion scattering), the consortium was able to correlate the performance of MOS devices with such factors as surface contamination and atomic-scale roughness. The consortium brings together complementary skills and a unique equipment base with which to pursue its objectives. The essential skills brought to the project include UHV cluster tool with in situ diagnostics (AEA Technology); electrical characterisation (IMEC); scanning tunnelling microscopy (Cambridge University); and advanced silicon cleaning technology (Wacker). Devices will be fabricated in the UHV cluster tool and characterised at each process step. The electrical properties of the devices will then be correlated with process parameters such as wet chemical cleaning procedures, contamination and silicon initial surface structure, and roughness. Structures will also be fabricated by conventional processing routes for comparison purposes. The results will be evaluated in terms of possible applications in current and future processing technologies. POTENTIAL The results of the ultra clean processing investigations will enable the development of improved VLSI fabrication techniques to be made. The observation of gate dielectric breakdown at fields as high as 40MV/cm over small areas is encouraging for the reliability of the thin gate oxides required for the next generations of CMOS devices. However, much work is still required to achieve improvements in MOS yields, including a better understanding of the effects of Si surface roughness and surface impurities in order to achieve improved breakdown values over large areas. Both the conducting AFM and the TOF-MEISS equipment developed in this programme are now available as commercial instrument packages. The IMEC cleaning procedure has been patented and exploitation routes are being persued at present. Ámbito científico natural scienceschemical sciencesinorganic chemistryinorganic compoundsnatural sciencesphysical sciencesastronomyplanetary sciencesplanetary geologynatural scienceschemical sciencesorganic chemistryhydrocarbonsnatural sciencesphysical sciencesopticsmicroscopynatural scienceschemical sciencesinorganic chemistrymetalloids Programa(s) FP3-ESPRIT 3 - Specific research and technological development programme (EEC) in the field of information technologies, 1990-1994 Tema(s) Data not available Convocatoria de propuestas Data not available Régimen de financiación Data not available Coordinador United Kingdom Atomic Energy Authority (UKAEA) Aportación de la UE Sin datos Dirección Culham Laboratory OX14 3DB Abingdon Reino Unido Ver en el mapa Coste total Sin datos Participantes (3) Ordenar alfabéticamente Ordenar por aportación de la UE Ampliar todo Contraer todo INTERUNIVERSITAIR MIKROELEKTRONICA CENTRUM Bélgica Aportación de la UE Sin datos Dirección KAPELDREEF, 75 3030 HEVERLEE Ver en el mapa Coste total Sin datos University of Cambridge Reino Unido Aportación de la UE Sin datos Dirección Free School Lane CB2 3RF Cambridge Ver en el mapa Coste total Sin datos Wacker Chemitronic Alemania Aportación de la UE Sin datos Dirección Johannes-Hess-Straße 24 84489 Burghausen Ver en el mapa Coste total Sin datos
