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A Mips Cruncher for a Distributed Concurrent Heterogeneous Simulation System

Objective

The objective of CHESS is to analyse the feasibility and application potential of a VHDL simulation system capable of 20 000 VHDL events per second per mips. The project is mainly focused on system level VHDL descriptions, considering not only a single IC but also a system composed of different components.
The feasibility and application potential of a verifiable hardware description language (VHDL) simulation system capable of 20000 VHDL events per second per MIPS have been investigated. The project is mainly focused on system level VHDL descriptions, considering not only a single integrated circuit (IC) but also a system composed of different components. The approach to the design of the simulation system is innovative under 2 aspects:
it is based on a parallel architecture whose nodes could be dedicated processors, standard processors, or workstations;
it adopts a distributed time simulation algorithm, which shows a much higher degree of parallelism than traditional approaches.

A benchmark suite to define the target application area has been developed. This suite reflects industrial needs. The benchmark suite is fundamental for the evaluation of different architectural alternatives and for the analysis of the most promising simulation algorithms.

A set of kernel tools for a VHDL simulation environment that could be retargetable for a wide range of parallel machines has been developed. These tools include a complete VHDL to C compiler, a set of run time routines, a sequential simulation kernel, and a parallel simulation kernel supporting conservative and optimistic distributed time algorithms.

An analysis system to evaluate the amount of parallelism which is available in a VHDL simulation has been developed. The main tool is based on the analysis of execution traces obtained by commercial simulators.
The approach to the design of the simulation system is innovative under two aspects:

- it is based on a parallel architecture whose nodes could be dedicated processors, standard processors, or workstations
- it adopts a distributed-time simulation algorithm, which shows a much higher degree of parallelism than traditional approaches.

Coordinator

UNIVERSITY OF GENOVA
Address
Via Dodecaneso 35
16146 Genova
Italy

Participants (4)

Daisy-Cadnetix
United Kingdom
Address
2,600 First Avenue
RG13 2PZ Newbury
GESELLSCHAFT FÜR SILIZIUM-ANWENDUNGEN UND CAD/CAT IN NIEDERSACHSEN
Germany
Address
Garbsener Landstraße 10
Hannover
Italtel Società Italiana Telecomunicazioni SpA
Italy
Address
Castelletto Di Settimo Milanese
20019 Milano
TECHNISCHE UNIVERSITEIT DELFT
Netherlands
Address
Mekelweg 4, 5031
2600 AG Delft