Periodic Reporting for period 1 - MeshAnalyzer (Analysis Tool for Mesh Design of Leading Edge Design of Integrated Circuits)
Reporting period: 2015-02-01 to 2015-07-31
• design chips with higher performance
• design chips with lower power consumption
• design chips with greater reliability
• reduce the cost of engineering the chips
• gain higher yield in production
• accelerate the time-to-market
The general objective of the proposed innovation project is to finalize and market a software tool that allows overcoming the limitations of the well-established tools of the few leading EDA (Electronic Design Automation) software companies.
The specific objective of the feasibility study is to finalize a prototype, including the documentation and preliminary marketing material. We also intend to contractually close partnerships with two leading IC design companies. We clarified the business plan.
• We have discussions going on with several semiconductor companies, who are interested by our technology. Those discussions are all under NDA. More than four visits to those customers have been carried out over the short period of 6 months.
• Because none of those companies is willing to share detailed data with us at this point in time, we have closed an additional contract with a semi-academic design house, Leti in France, which allows us to move the academic prototype to an industrial level.
• We have determined the necessary resources.
• We have analysed the market with respect to the potential customer base, the potential competitors and we especially have had a look at the current dynamics in the market.
• We have determined the price and the options of the future tool.
• We have developed marketing material, which will be useful to move on to the next step.
This project furthermore allows circuit designers to switch totally or partly to the use of clock meshes or combinations of clock trees and clock meshes. The tool will allow reducing the current design time (between 9 and 24 months for a leading edge design) by up to 40%, because the timing is correct by construction using clock meshes. We also will immediately join the analysis of reliability to the package in order to have a clear added value.
Because this is an enabling technology for energy savings even on low power circuits, this approach becomes very interesting to designers of processors for mobile applications, like smart phones and tablets. Due to an important pressure of the market to have less energy-hungry processors at a very short time of development, we believe that this technology will be very interesting to a number of important IC designers.
As we became leader on the niche market of netlist reduction technology for physical verification, we believe that we can become leader of this design technology, and bring back to Europe a part of the EDA market, which is today basically a US-based market.