Analysis Tool for Mesh Design of Leading Edge Design of Integrated Circuits

Project Information

MeshAnalyzer

Grant agreement ID: 662704

DOI

10.3030/662704

Project closed

EC signature date 29 January 2015

Start date 1 February 2015

End date 31 July 2015

Funded under

• INDUSTRIAL LEADERSHIP - Leadership in enabling and industrial technologies - Information and Communication Technologies (ICT)

Total cost

€ 71 429,00

EU contribution

€ 50 000,00

Coordinated by

EDXACT
France

Periodic Reporting for period 1 - MeshAnalyzer (Analysis Tool for Mesh Design of Leading Edge Design of Integrated Circuits)

Reporting period: 2015-02-01 to 2015-07-31

Summary of the context and overall objectives of the project

The goal of this proposal is to finalize a new CAD (computer aided design) software tools for the reliable design of modern electronic integrated circuits. The tool suite will be dedicated to the design and analysis of clock meshes and nets. Users of the tools will be designers of integrated circuits. In a first step, we will address designers of chips for hardware infrastructure; in a second step we will address designers of chips for mobile devices. The new software tool will allow circuit designers to

• design chips with higher performance
• design chips with lower power consumption
• design chips with greater reliability
• reduce the cost of engineering the chips
• gain higher yield in production
• accelerate the time-to-market

The general objective of the proposed innovation project is to finalize and market a software tool that allows overcoming the limitations of the well-established tools of the few leading EDA (Electronic Design Automation) software companies.

The specific objective of the feasibility study is to finalize a prototype, including the documentation and preliminary marketing material. We also intend to contractually close partnerships with two leading IC design companies. We clarified the business plan.

Work performed from the beginning of the project to the end of the period covered by the report and main results achieved so far

We conclude that phase 1 of the project has allowed us to move a step forward towards our goal and that we have fully achieved our goals in phase 1:

• We have discussions going on with several semiconductor companies, who are interested by our technology. Those discussions are all under NDA. More than four visits to those customers have been carried out over the short period of 6 months.
• Because none of those companies is willing to share detailed data with us at this point in time, we have closed an additional contract with a semi-academic design house, Leti in France, which allows us to move the academic prototype to an industrial level.
• We have determined the necessary resources.
• We have analysed the market with respect to the potential customer base, the potential competitors and we especially have had a look at the current dynamics in the market.
• We have determined the price and the options of the future tool.
• We have developed marketing material, which will be useful to move on to the next step.

Progress beyond the state of the art and expected potential impact (including the socio-economic impact and the wider societal implications of the project so far)

The project firstly innovates on a technical level: we will finalize a tool necessary to analyse the timing of clock meshes and clock nets under reliability constraints. This does not exist today with acceptable accuracy and sufficient capacity.

This project furthermore allows circuit designers to switch totally or partly to the use of clock meshes or combinations of clock trees and clock meshes. The tool will allow reducing the current design time (between 9 and 24 months for a leading edge design) by up to 40%, because the timing is correct by construction using clock meshes. We also will immediately join the analysis of reliability to the package in order to have a clear added value.

Because this is an enabling technology for energy savings even on low power circuits, this approach becomes very interesting to designers of processors for mobile applications, like smart phones and tablets. Due to an important pressure of the market to have less energy-hungry processors at a very short time of development, we believe that this technology will be very interesting to a number of important IC designers.

As we became leader on the niche market of netlist reduction technology for physical verification, we believe that we can become leader of this design technology, and bring back to Europe a part of the EDA market, which is today basically a US-based market.

clock distribution network using a clock mesh