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Novel Parallel Algorithms and New Real-Time VLSI Architectural Methodologies 2

Objective

A first aim of NANA 2 is to develop new real-time parallel algorithms and new VLSI architectures for a variety of applications, both in real-time multi-dimensional signal processing and in numerical processing. Here, a clear need exists for novel parallel algebraic and numerical kernels and the combinations of kernels into complete algorithms.

In order to allow future design of complex high throughput applications, NANA 2 also explores novel technologies in the area of architectural synthesis techniques, which create a suitable architecture from a behavioural specification.
Research has been carried out in order to develop new real time parallel algorithms and new very large scale integration (VLSI) architectures for a variety of applications, both in real time multidimensional signal processing and in numerical processing. Here, a clear need exists for novel parallel algebraic and numerical kernels and the combinations of kernels into complete algorithms.
In order to allow future design of complex high throughput applications, novel technologies in the area of architectural synthesis techniques have been explored, which create a suitable architecture from a behavioural specification.

The following major results have been achieved:
design and implemention of new algorithms for rendering and for skeletonization (scheduling techniques for loop nests with uniform or affine dependences have also been investigated);\the proposition of practical parallel recursive updating algorithms for adaptive antenna applications, namely robust linearly constrained minimum variance beamforming and direction of arrival estimation for multiple wide band emitters;
generalization of the Hankel-norm approximation problem in the context of model reduction to the time varying case (a parallel pipelined multiprocessor system has also been realised for the rendering of photo realistic scenes in interaction time and the implementation of the design tools has been extended);
completion of the study and implementation of several new transformations in the Alpha array synthesis environment, including the link to VLSI chip generation. (Alpha is now also available under Mathematica);
coupling of the memory optimization techniques to a behavioural simulator, resulting in significant simulation speed-ups (also the models used for memory management have been extended towards variable rate image processing applications).
APPROACH AND METHODS

The NANA 2 approach will continue on the same track as that of NANA (action 3280), with the work divided into two areas:

- Novel algorithms for parallel architectures. These algorithms will be developed for time-critical and/or space-critical practical problems. NANA2 will emphasise a class of sophisticated algorithms which combine several submodules. In this way, the approach is better targeted to complete applications, compared to NANA.

- New architectural design methodologies and synthesis techniques : appropriate subsets of architectural features, ie specific "target architectural styles" will be selected, depending on the application field in mind. The different novel algorithms to be developed have specific characteristics which can be matched with specific features in different architectural styles. Several basic transformations, common to all synthesis techniques, will be studied. At the same time some prototype synthesis tools will be developed, loosely coupled in a common work-bench approach.

POTENTIAL

The work is of major importance for the development of efficient systems in many fields such as image and seismic processing, video, robotics, radar, sonar, telecommunication, factory automation, biomedical technology and adaptive beamforming. Studying the systems in terms of both novel parallel algorithms and efficient new architectural methodologies will allow to map these systems onto future VLSI or parallel processor realisations with smaller design and production costs.

Coordinator

INTERUNIVERSITAIR MIKROELEKTRONICA CENTRUM
Address
Kapeldreef, 75
3030 Heverlee
Belgium

Participants (4)

Institut National de Recherches en Informatique et en Automatique (INRIA)
France
Address
Domaine De Voluceau Rocquencourt
78153 Le Chesnay
KATHOLIEKE UNIVERSITEIT LEUVEN
Belgium
Address
Tervuursevest, 101
3000 Leuven
TECHNISCHE UNIVERSITEIT DELFT
Netherlands
Address
Landbergstraat, 35
2628 CE Delft
École Normale Supérieure de Lyon
France
Address
46 Allée D'italie
69364 Lyon