Piezoelectronic Transduction Memory Device

Objective

Computer clock speeds have not increased since 2003, creating a challenge to invent a successor to CMOS technology able to resume performance improvement. The key requirements for a viable alternative are scalability to nanoscale dimensions – following Moore’s Law – and simultaneous reduction of line voltage in order to limit switching power. Achieving these two aims for both transistors and memory allows clock speed to again increase with dimensional scaling, a result that would have great impact across the IT industry.
We propose to demonstrate an entirely new low-voltage, memory element that makes use of internal transduction in which a voltage state external to the device is converted to an internal acoustic signal that drives an insulator-metal transition. Modelling based on the properties of known materials at device dimensions on the 15 nm scale predicts that this mechanism enables device operation at voltages an order of magnitude lower than CMOS technology while achieving 10GHz operating speed; power is thus reduced two orders.

Field of science

• /social sciences/law

Programme(s)

• H2020-EU.2.1.1. - INDUSTRIAL LEADERSHIP - Leadership in enabling and industrial technologies - Information and Communication Technologies (ICT)

Topic(s)

• ICT-25-2015 - Generic micro- and nano-electronic technologies

Call for proposal

H2020-ICT-2015
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Funding Scheme

Coordinator

Participants (12)