Objective
Computer clock speeds have not increased since 2003, creating a challenge to invent a successor to CMOS technology able to resume performance improvement. The key requirements for a viable alternative are scalability to nanoscale dimensions – following Moore’s Law – and simultaneous reduction of line voltage in order to limit switching power. Achieving these two aims for both transistors and memory allows clock speed to again increase with dimensional scaling, a result that would have great impact across the IT industry.
We propose to demonstrate an entirely new low-voltage, memory element that makes use of internal transduction in which a voltage state external to the device is converted to an internal acoustic signal that drives an insulator-metal transition. Modelling based on the properties of known materials at device dimensions on the 15 nm scale predicts that this mechanism enables device operation at voltages an order of magnitude lower than CMOS technology while achieving 10GHz operating speed; power is thus reduced two orders.
Fields of science
Call for proposal
H2020-ICT-2015
See other projects for this call
Funding Scheme
RIA - Research and Innovation actionCoordinator
NW1 3BT London
United Kingdom
Participants (12)
52068 Aachen
TW11 0LW Middlesex
Participation ended
7034 Trondheim
80539 Munchen
9000 Gent
8803 Rueschlikon
7521 PE Enschede
20360 Turku
Participation ended
EH8 9YL Edinburgh
GU9 9QT Farnham
8600 Dubendorf
7034 Trondheim