Objective
Computer clock speeds have not increased since 2003, creating a challenge to invent a successor to CMOS technology able to resume performance improvement. The key requirements for a viable alternative are scalability to nanoscale dimensions – following Moore’s Law – and simultaneous reduction of line voltage in order to limit switching power. Achieving these two aims for both transistors and memory allows clock speed to again increase with dimensional scaling, a result that would have great impact across the IT industry.
We propose to demonstrate an entirely new low-voltage, memory element that makes use of internal transduction in which a voltage state external to the device is converted to an internal acoustic signal that drives an insulator-metal transition. Modelling based on the properties of known materials at device dimensions on the 15 nm scale predicts that this mechanism enables device operation at voltages an order of magnitude lower than CMOS technology while achieving 10GHz operating speed; power is thus reduced two orders.
Fields of science
- humanitiesartsmodern and contemporary artradio and television
- natural sciencescomputer and information sciencesinternet
- engineering and technologyelectrical engineering, electronic engineering, information engineeringelectronic engineeringsensors
- engineering and technologyelectrical engineering, electronic engineering, information engineeringelectrical engineeringpiezoelectrics
- social scienceslaw
Call for proposal
H2020-ICT-2015
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Funding Scheme
RIA - Research and Innovation actionCoordinator
NW1 3BT London
United Kingdom
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Participants (12)
52068 Aachen
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TW11 0LW Middlesex
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7034 Trondheim
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80539 Munchen
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9000 Gent
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8803 Rueschlikon
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7521 PE Enschede
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20360 Turku
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EH8 9YL Edinburgh
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GU9 9QT Farnham
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8600 Dubendorf
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7034 Trondheim
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