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High-Performance Real-time Architectures for Low-Power Embedded Systems

Deliverables

Final Board

The final board: one for the automotive (integrating application-specific hardware), one for the avionic application. Proper exploitation of potential FPGA modules and accelerators available on the boards.

Multi-OS integration and Virtualization

This deliverable resulting from Task 4.3 is a package containing the additional software components for the concurrent execution of Linux and ERIKA Enterprise on the same SoC, and for the synchronization and communication between the two OSs. The deliverable also contains a technical user manual explaining how to install and use the provided package.

Optimized runtime for parallel heterogeneous platforms

The final prototype of the heterogeneous runtime system, plus a report describing the architecture, design principle, main features and results obtained on a first set of benchmarks, in comparison with state-of-the art solutions.

Optimized support for predictability in the accelerator programing environment

The final prototype and a report describing the enhancements implemented for supporting predictability in the target programming model. Support for specification of real-time constraints and interface to RT-analysis tools and environment will be detailed.

Real-time Linux - final

This deliverable is a software package containing the final version of the real-time Linux OS for the reference many-core platform, developed in Tasks 4.1. The deliverable also contains a technical user manual explaining how to install and use the provided package.

Lightweight RTOS - final

This deliverable is a software package containing the final version of the lightweight RTOS for the reference many-core platform, developed in Tasks 4.2. The deliverable also contains a technical user manual explaining how to install and use the provided package.

Detailed Characterization of Platforms

A detailed characterization / model of the performance and energy consumption of the chosen platforms that can be used in the development and evaluation of the schedulers in WP5.

Programming Model(s) analysis and selection

Specification of the chosen programming model(s), including a survey on existing support on the platforms.

Project management plan

Provides detailed guidelines and project management plan. It includes the initial Data Management Plan.

Scheduling Algorithm for Parallel Accelerators

Specification of a scheduling algorithm for execution on accelerators that optimizes accelerator performance and minimizes energy consumption, subject to real-time constraints.

Integrated Schedulability Analysis

Schedulability analysis that considers the combination of the proposed scheduling algorithm executing on the host and on the accelerators.

Year 1 Periodic report

Periodic report after year1. It includes Data Management Report.

Open source results

This deliverable will show the final plan for open source exploitation of the software produced in the project, together with a description of the dissemination activities performed to promote it.

Final exploitation plan

This deliverable will contain the final market analysis for the domains targeted by the project, and will show the results achieved, that is, how the outcomes of HERCULES were/will be pushed in the target market areas. It will also contain the specific exploitation plans by all partners.

Final dissemination report

A final summary of the dissemination activities performed in the project.

Open source strategy plan

This deliverable will be a first draft of the exploitation strategy for the open source software: e.g., how it will be made available, under which license, and possible dissemination activities (presentations, tutorials) for it.

Final Periodic report

Final report of the project. It will include an overview of all outcomes of HERCULES, and it will refer to single final deliverables of all work-packages for details. It includes Data Management Report.

Power-Aware Scheduling Algorithm for Host

Specification of a real-time scheduling algorithm for execution on the host that considers CPU scheduling as well as accesses to shared resources, such as memories, with the objective of minimizing power under real-time constraints.

Specification of Hardware Platforms

Report detailing the results from the platform evaluation and selection for each application (domain).

Application Requirements

This deliverable will list the application requirements and meaningful performance metrics of each application, taking into account the specific application domain (avionics and automotive).

Validation Report

A report of all validation activities on the reference applications running on the specific target architectures, describing the set of experiments performed to validate the use cases under each metric (e.g., energy consumption, performance/cost, predictability), and the improvements achieved with respect to the state-of-the-art and to the initial analysis performed in T1.1, and described in D1.1.

Collaboration and Communication Tools

A report describing all the tools set up to promote and support cooperation among partners.

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Publications

Energy-aware real-time scheduling in the linux kernel

Author(s): Claudio Scordino, Luca Abeni, Juri Lelli
Published in: Proceedings of the 33rd Annual ACM Symposium on Applied Computing - SAC '18, 2018, Page(s) 601-608
DOI: 10.1145/3167132.3167198

SiGAMMA - server based integrated GPU arbitration mechanism for memory accesses

Author(s): Nicola Capodieci, Roberto Cavicchioli, Paolo Valente, Marko Bertogna
Published in: Proceedings of the 25th International Conference on Real-Time Networks and Systems - RTNS '17, 2017, Page(s) 48-57
DOI: 10.1145/3139258.3139270

GPUguard: towards supporting a predictable execution model for heterogeneous SoC

Author(s): Bjorn Forsberg, Andrea Marongiu, Luca Benini
Published in: Proceedings of the Conference on Design, Automation & Test in Europe, 2017, Page(s) 318-321
DOI: 10.3929/ethz-b-000222912

HERO: Heterogeneous Embedded Research Platform for Exploring RISC-V Manycore Accelerators on FPGA

Author(s): Kurth, Andreas; Vogel, Pirmin; Capotondi, Alessandro; Marongiu, Andrea; Benini, Luca
Published in: Proceedings of Computer Architecture Research with RISC-V Workshop (CARRV' 17), Issue 11, 2017
DOI: 10.3929/ethz-b-000219249

Scalable and Efficient Virtual Memory Sharing in Heterogeneous SoCs with TLB Prefetching and MMU-Aware DMA Engine

Author(s): Andreas Kurth, Pirmin Vogel, Andrea Marongiu, Luca Benini
Published in: 2018 IEEE 36th International Conference on Computer Design (ICCD), 2018, Page(s) 292-300
DOI: 10.1109/iccd.2018.00052

Combining PREM compilation and ILP scheduling for high-performance and predictable MPSoC execution

Author(s): Joel Matějka, Björn Forsberg, Michal Sojka, Zdeněk Hanzálek, Luca Benini, Andrea Marongiu
Published in: Proceedings of the 9th International Workshop on Programming Models and Applications for Multicores and Manycores - PMAM'18, 2018, Page(s) 11-20
DOI: 10.1145/3178442.3178444

Convolutional Neural Networks on Embedded Automotive Platforms: A Qualitative Comparison

Author(s): Gianluca Brilli, Paolo Burgio, Marko Bertogna
Published in: 2018 International Conference on High Performance Computing & Simulation (HPCS), 2018, Page(s) 496-499
DOI: 10.1109/hpcs.2018.00084

On the Cost of Freedom From Interference in Heterogeneous SoCs

Author(s): Björn Forsberg, Luca Benini, Andrea Marongiu
Published in: Proceedings of the 21st International Workshop on Software and Compilers for Embedded Systems - SCOPES '18, 2018, Page(s) 31-34
DOI: 10.1145/3207719.3207735

HePREM: Enabling predictable GPU execution on heterogeneous SoC

Author(s): Bjorn Forsberg, Luca Benini, Andrea Marongiu
Published in: 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2018, Page(s) 539-544
DOI: 10.23919/date.2018.8342066

The key role of memory in next-generation embedded systems for military application

Author(s): Ignacio Sañudo, Paolo Cortimiglia, Luca Miccio, Marco Solieri, Paolo Burgio, Christian Di Biagio, Franco Felici, Giovanni Nuzzo and Marko Bertogna
Published in: Proceedings of International Conference in Software Engineering for Defence Applications,in Advances in Intelligent Systems and Computing, 2019

A Perspective on Safety and Real-Time Issues for GPU Accelerated ADAS

Author(s): Ignacio Sanudo Olmedo, Nicola Capodieci, Roberto Cavicchioli
Published in: IECON 2018 - 44th Annual Conference of the IEEE Industrial Electronics Society, 2018, Page(s) 4071-4077
DOI: 10.1109/iecon.2018.8591540

Deadline-Based Scheduling for GPU with Preemption Support

Author(s): Nicola Capodieci, Roberto Cavicchioli, Marko Bertogna, Aingara Paramakuru
Published in: 2018 IEEE Real-Time Systems Symposium (RTSS), 2018, Page(s) 119-130
DOI: 10.1109/rtss.2018.00021

Work-in-Progress: NVIDIA GPU Scheduling Details in Virtualized Environments

Author(s): Nicola Capodieci, Roberto Cavicchioli, Marko Bertogna
Published in: 2018 International Conference on Embedded Software (EMSOFT), 2018, Page(s) 1-3
DOI: 10.1109/emsoft.2018.8537220

Target following on nano-scale Unmanned Aerial Vehicles

Author(s): Daniele Palossi, Jaskirat Singh, Michele Magno, Luca Benini
Published in: 2017 7th IEEE International Workshop on Advances in Sensors and Interfaces (IWASI), 2017, Page(s) 170-175
DOI: 10.1109/IWASI.2017.7974242

A Software Stack for Next-Generation Automotive Systems on Many-Core Heterogeneous Platforms

Author(s): Paolo Burgio, Marko Bertogna, Ignacio Sanudo Olmedo, Paolo Gai, Andrea Marongiu, Michal Sojka
Published in: 2016 Euromicro Conference on Digital System Design (DSD), 2016, Page(s) 55-59
DOI: 10.1109/DSD.2016.84

On the Accuracy of Near-Optimal CPU-Based Path Planning for UAVs

Author(s): Daniele Palossi, Andrea Marongiu, Luca Benini
Published in: Proceedings of the 20th International Workshop on Software and Compilers for Embedded Systems - SCOPES '17, 2017, Page(s) 85-88
DOI: 10.1145/3078659.3079072

Towards predictable execution model on ARM-based heterogeneous platforms

Author(s): Premysl Houdek, Michal Sojka, Zdenek Hanzalek
Published in: 2017 IEEE 26th International Symposium on Industrial Electronics (ISIE), 2017, Page(s) 1297-1302
DOI: 10.1109/ISIE.2017.8001432

Exploring Single Source Shortest Path Parallelization on Shared Memory Accelerators

Author(s): Daniele Palossi, Andrea Marongiu
Published in: Proceedings of the 19th International Workshop on Software and Compilers for Embedded Systems - SCOPES '16, 2016, Page(s) 197-200
DOI: 10.1145/2906363.2915925

Ultra low-power visual odometry for nano-scale unmanned aerial vehicles

Author(s): Daniele Palossi, Andrea Marongiu, Luca Benini
Published in: Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017, 2017, Page(s) 1647-1650
DOI: 10.23919/DATE.2017.7927257

Adaptive Coordination in Autonomous Driving: Motivations and Perspectives

Author(s): Marko Bertogna, Paolo Burgio, Giacomo Cabri, Nicola Capodieci
Published in: 2017 IEEE 26th International Conference on Enabling Technologies: Infrastructure for Collaborative Enterprises (WETICE), 2017, Page(s) 15-17
DOI: 10.1109/WETICE.2017.45

Self-Sustainability in Nano Unmanned Aerial Vehicles - A Blimp Case Study

Author(s): Daniele Palossi, Andres Gomez, Stefan Draskovic, Kevin Keller, Luca Benini, Lothar Thiele
Published in: Proceedings of the Computing Frontiers Conference on ZZZ - CF'17, 2017, Page(s) 79-88
DOI: 10.1145/3075564.3075580

On the effectiveness of OpenMP teams for cluster-based many-core accelerators

Author(s): Alessandro Capotondi, Andrea Marongiu
Published in: 2016 International Conference on High Performance Computing & Simulation (HPCS), 2016, Page(s) 667-674
DOI: 10.1109/HPCSim.2016.7568399

An energy-efficient parallel algorithm for real-time near-optimal UAV path planning

Author(s): Daniele Palossi, Michele Furci, Roberto Naldi, Andrea Marongiu, Lorenzo Marconi, Luca Benini
Published in: Proceedings of the ACM International Conference on Computing Frontiers - CF '16, 2016, Page(s) 392-397
DOI: 10.1145/2903150.2911712

A static scheduling approach to enable safety-critical OpenMP applications

Author(s): Alessandra Melani, Maria A. Serrano, Marko Bertogna, Isabella Cerutti, Eduardo Quinones, Giorgio Buttazzo
Published in: 2017 22nd Asia and South Pacific Design Automation Conference (ASP-DAC), 2017, Page(s) 659-665
DOI: 10.1109/ASPDAC.2017.7858399

Efficient Virtual Memory Sharing via On-Accelerator Page Table Walking in Heterogeneous Embedded SoCs

Author(s): Pirmin Vogel, Andreas Kurth, Johannes Weinbuch, Andrea Marongiu, Luca Benini
Published in: ACM Transactions on Embedded Computing Systems, Issue 16/5s, 2017, Page(s) 1-19, ISSN 1539-9087
DOI: 10.1145/3126560

Multi-Variant Scheduling of Critical Time-Triggered Communication in Incremental Development Process: Application to FlexRay

Author(s): Jan Dvorak, Zdenek Hanzalek
Published in: IEEE Transactions on Vehicular Technology, Issue 68/1, 2019, Page(s) 155-169, ISSN 0018-9545
DOI: 10.1109/tvt.2018.2879920

Exploring Shared Virtual Memory for FPGA Accelerators with a Configurable IOMMU

Author(s): Pirmin Vogel, Andrea Marongiu, Luca Benini
Published in: IEEE Transactions on Computers, 2018, Page(s) 1-1, ISSN 0018-9340
DOI: 10.1109/tc.2018.2879080

Extending the Lifetime of Nano-Blimps via Dynamic Motor Control

Author(s): Daniele Palossi, Andres Gomez, Stefan Draskovic, Andrea Marongiu, Lothar Thiele, Luca Benini
Published in: Journal of Signal Processing Systems, Issue 91/3-4, 2019, Page(s) 339-361, ISSN 1939-8018
DOI: 10.1007/s11265-018-1343-1

Combining PREM Compilation and Static Scheduling for High-Performance and Predictable MPSoC Execution

Author(s): Joel Matějka, Björn Forsberg, Michal Sojka, Přemysl Šůcha, Luca Benini, Andrea Marongiu, Zdeněk Hanzálek
Published in: Parallel Computing, 2018, ISSN 0167-8191
DOI: 10.1016/j.parco.2018.11.002

Real-time and energy efficiency in Linux

Author(s): Claudio Scordino, Luca Abeni, Juri Lelli
Published in: ACM SIGAPP Applied Computing Review, Issue 18/4, 2019, Page(s) 18-30, ISSN 1559-6915
DOI: 10.1145/3307624.3307627

A design flow for supporting component-based software development in multiprocessor real-time systems

Author(s): Alessandro Biondi, Giorgio Buttazzo, Marko Bertogna
Published in: Real-Time Systems, Issue 54/4, 2018, Page(s) 800-829, ISSN 0922-6443
DOI: 10.1007/s11241-018-9301-3

Time-Triggered Co-Scheduling of Computation and Communication with Jitter Requirements

Author(s): Anna Minaeva, Benny Akesson, Zdenek Hanzalek, Dakshina Dasari
Published in: IEEE Transactions on Computers, 2017, Page(s) 1-1, ISSN 0018-9340
DOI: 10.1109/TC.2017.2722443

GPU-Accelerated Real-Time Path Planning and the Predictable Execution Model

Author(s): Björn Forsberg, Daniele Palossi, Andrea Marongiu, Luca Benini
Published in: Procedia Computer Science, Issue 108, 2017, Page(s) 2428-2432, ISSN 1877-0509
DOI: 10.1016/j.procs.2017.05.219

Accelerated Visual Context Classification on a Low-Power Smartwatch

Author(s): Francesco Conti, Daniele Palossi, Renzo Andri, Michele Magno, Luca Benini
Published in: IEEE Transactions on Human-Machine Systems, 2017, Page(s) 1-12, ISSN 2168-2291
DOI: 10.1109/THMS.2016.2623482

A software stack for next-generation automotive systems on many-core heterogeneous platforms

Author(s): Paolo Burgio, Marko Bertogna, Nicola Capodieci, Roberto Cavicchioli, Michal Sojka, Přemysl Houdek, Andrea Marongiu, Paolo Gai, Claudio Scordino, Bruno Morelli
Published in: Microprocessors and Microsystems, Issue 52, 2017, Page(s) 299-311, ISSN 0141-9331
DOI: 10.1016/j.micpro.2017.06.016