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Intelligent Memories that Perform Inference with the Physics of Nanodevices

Periodic Reporting for period 2 - NANOINFER (Intelligent Memories that Perform Inference with the Physics of Nanodevices)

Reporting period: 2018-09-01 to 2020-02-29

Cognitive tasks are increasingly necessary in modern electronics. The energy efficiency of associated algorithms, which rely on abundant stored parameters, is severely limited by the separation of computation and memory elements in conventional computers. NANOINFER is directly addressing this challenge by developing intelligent memory chips that natively perform both memory and computing functions, using CMOS and emerging nanodevices. These chips perform Bayesian inference or neural networks algorithms, which allow cognitive-type reasoning. The project includes theoretical investigations as well as intelligent memory chip designs, supported by proof-of-concept experimental demonstrations. The proposed architectures, based on spintronic and memristive memories, maximize energy efficiency by leveraging the complex physics of these emerging devices for inference operations and the storage of model parameters, and by minimizing exchanges between computation units and memory. Inference will be performed using sampling algorithms and compute-in-memory functions that allow tackling difficult problems and are robust to nanodevice imperfections. NANOINFER also develops learning-capable chips, able to adapt the stored Bayesian or neural network model to new data, still leveraging the complex physics of nanodevices.

As the intelligent memories developed within NANOINFER are very low power, their use will be possible directly within smart devices, therefore reducing their reliance on data centers. This can bring massive energy saving, avoiding all the energy cost associated with the communication between smart devices and data centers. A major application is systems that have to process sensory-motor information (e.g. robots), and all systems which have to fuse information coming from diverse sensors and/or prior information (e.g. smart sensors and biomedical chips), or vehicle driver assistance or automation. The possibility to have learning in the intelligent memory can also provide an extreme adaptability to the smart devices. The intelligent memory chips also provide features essential to data centers, which must typically infer information from large quantities of stored data. NANOINFER thus opens a way for extremely energy efficient chips for data centers (IT now represents 10% of electricity consumption worldwide, a number which is expected to grow).
We have first explored nanodevices which can be used within natively intelligent memories. Hafnium oxide based memories appeared as excellent candidates for storing information, as they are compatible with current microelectronics technology, scalable, reliable. They also feature a possibility to adapt the stored value, providing an appropriate substrate for learning. We also realized that when used in natively intelligent memories, hafnium oxide based memories may be used in regimes different from their traditional applications, with high benefits in terms of energy efficiency and reliability. We have also investigated spin electronics-based nanodevices called superparamagnetic tunnel junctions. These intrinsically stochastic devices can provide fantastic basic elements for the sampling operation, an important part of most of our natively intelligent memories designs.

Second, we have designed full natively intelligent memories associating nanodevices and conventional transistors. This design work involved the codesign of adapted machine learning architectures, and circuits and systems, while simultaneously testing the appropriateness of the ideas on real arrays of nanodevices. Our designs implement Bayesian inference and a class of neural networks specially adapted to natively intelligent memories: binarized neural networks. These designs achieve outstanding energy efficiency through three mechanisms. They collocate logic and memory and requiring extremely minimal data movement within the system. They rely on highly simplified arithmetic. Finally, they exploit nanodevices in adapted regimes, where they are not deterministic. We have also proposed a first approach to provide these memories with a learning features. In our approach, the nanodevices are used in an analog manner, but the transistors are used solely in a digital manner, requiring very little overhead and no formal conversion between the analog and the digital worlds.
We have proposed, and demonstrated in proof-of-concept experiments, how hafnium oxide devices and superparamagnetic tunnel junctions may be used to implement machine learning schemes in conditions where the devices exhibit maximal energy efficiency. We also have now designed and taped out (using a hybrid CMOS/nano technology) full systems implementing natively intelligent memories, incorporating thousands of nanodevices and transistors. Our designs mix ideas coming from device physics and digital design in a highly original way entirely oriented toward maximizing energy efficiency: we collocate logic and memory and embrace the unreliability of nanodevices without trying to correct it. The second phase of the project will consist in testing these systems experimentally, and in scaling them to larger problems. A major part of our work will also consist in extending their learning capabilities. Several types of learning approaches will be investigating and compared, taking inspiration from recent developments in machine learning, and by addressing questions coming from device physics, circuits and system design, and applications in parallel. We are also developing a specific nanodevice for these approaches.
Layout of a Bayesian natively intelligent memory using a hybrid CMOS/nanodevice technology