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Enabling flexible integrated circuits and applications

Periodic Reporting for period 4 - FLICs (Enabling flexible integrated circuits and applications)

Reporting period: 2021-07-01 to 2021-12-31

The goal of this FLICs proposal was to develop disruptive technology and ground-breaking design innovations with amorphous oxide TFTs on plastic substrates, targeting large scale or very large scale flexible integrated circuits with unprecedented characteristics in terms of power consumption, supply voltage and operating speed, for applications in IoT and wearable healthcare sensor patches.

Throughout the project, we investigated on different logic styles which take advantage of the transistor’s unique properties. We introduced new logic styles, “quasi-CMOS” or “cross-over logic” and ‘dual-input pseudo-CMOS” logic. The first logic style drastically decreases the power consumption of unipolar logic gates in a novel way by taking advantage of dynamic backgate driving and of the transistor’s unique low off-state leakage current, without compromising on switching speed. The second logic style takes advantage of having backgate terminal to reduce the number of pull-down transistors in NOR-based logic gates. Therefore, a 24% reduction in the number of TFTs in digital circuits is achieved. A third logic style that was introduced is dual-stage resistive load, in order to increase robustness of standard resistive load logic. Finally, we have been introducing a load mimicking the p-type, which is very important for analog electronics based on IGZO transistors. Those logic styles will be an enabler to increase future integration density for the flexible electronics society.

As introduced in the original proposal, we explored downscaling of the transistor’s dimensions, while remaining compatible with upscaling to large-area manufacturing platforms and as such introduce Moore’s law on flex. This enables to improve the energy-delay product significantly and therefore pave the way to novel application areas. Scaling occurred down to 800nm, which is today state-of-the-art for flexible IGZO-based electronics. In addition, we started exploring Si CMOS back-end-of-line (BEOL) transistors as a prospect for future research directions. The designs have been made; however, manufacturing of those transistors is a long trajectory, therefore, at the end of the ERC proposal, only initial results are present. Those are very promising, as they show fully operating ring oscillators with transistors exhibiting gate lengths much below 800nm.

Finally, we investigated novel ultralow-power design techniques on system-level and improved the custom-made digital design flow for thin-film technologies, while exploiting the novel logic gates. Combining all these low-power and improved energy-delay options would pave the way for the realization of unprecedented flexible VLSI circuits. The application areas that are envisioned in this project are flexible IoT communication chip, metal-oxide based wearable healthcare patches and microprocessor cores. At the end of the project, we have demonstrated the fastest 8-bit flexible microprocessor circuit operating at 71.4kHz clock speed and including more than 16000 transistors. This has been a milestone towards flexible VLSI circuits and proven the methodologies followed in FLICs project. During the project, we teamed up with Prof E. Cantatore, who is an expert in analog electronics. Together with our PhD teams, we have been able to realize the world-first ECG patch completely based on IGZO electronics
The project was defined in three sub-tasks: (1) novel logic gates; (2) technology scaling and (3) technology-aware design.

In terms of the first subtask, we have been very active on the logic style analysis with a strong emphasis on low-power unipolar logic gates. We have been able to reduce the inherently present static leakage current of inverters. The result of this route has been recently published as crossover logic, yielding a fivefold reduction in power consumption. Besides this novel circuit architecture, we have improved the power consumption of regular circuit topologies necessary to enable capacitive readout circuits. The aforementioned circuit consumed less than 160nW. Another logic style was the dual-stage resistive load logic, which led to a higher performance and robustness compared to conventional resistor-load logic style. This has been presented at the FLEPS 2021 conference. Finally, we explored and published another logic style focusing on area reduction based on the smart implementation of the backgate as input gate. This work predicted to reduce 2116 transistors for an 8-bit microprocessor. This has been published at ESSCIRC 2021.

The second sub-task focuses on the introduction of a Moore’s law on flex roadmap. We have pursuing downscaling until 1.5µm in phase I. As a result, the 1.5µm transistors embedded in a ring oscillator yielded the fastest reported metal-oxide based circuit exhibiting a stage delay of only 2.4ns on flexible substrates. This lead to the world-first NFC tag based on IGZO, published at ISSCC and Nature Electronics. As a next step, we focused on sub-micrometer transistor and reached succesfully in-house 800nm. However, as yield is very important, we teamed up with PragmatIC, a UK foundry who offers 800nm transistors. We continued to explore the FLICs roadmap in that technology. This has lead to several high-level outputs, of which one of them is surely the 8-bit flexible microprocessor, which was published at last ISSCC and will receive even a Nature Electronics highlight article! Besides the regular routes, we have been evaluating options to downscale even further. Imec is working on a BEOL IGZO technology for deep sub-micron memory applications. We have been collaborating with those teams to attach the FLICS roadmap perspective to their transistors. The main target is to proof that sub-micron IGZO transistors can provide very high speeds and low leakage currents. As this research activity is very labour-intense and takes time to develop these transistors, the full and final conclusions are not yet ready at the time of writing. Nonetheless, the initial results have shown promising indications that the ring-oscillators would operate successfully. We expect in the next few months to have this characterisation completed.

The last sub-task innovates at system level design, enabling new applications for this technology. The first real application that was realized is the world-first IGZO-based NFC tag due to a few key achievements within this project: (1) downscaling of the self-aligned technology yielding NFC-compatible operating voltages and inverter delays enabling direct clock recovery; (2) introducing low-power design technique like logic style partitioning and optimization for speed, robustness and low power. The NFC tag was well-received by the TFT community, leading to an ISSCC paper, an invited perspective article in Nature Electronics and several invited talks at conferences. In terms of low power electronics, we evaluated the opportunities for ultra-low power consumption and realized a touchscreen tag (in colalboration with the EU project CAPID). The demonstrator was widely accepted in the society and has been published in Nature Electronics.

The second application window that was envisioned are healthcare patches and sensor-node IoT devices. In this field, the team has worked on analog-to-digital converters as key circuit blocks for such systems, which are published in several papers. Also, we teamed up with TUe Prof. E. Cantatore to develop the world-first IGZO-based ECG patch, which was published in Nature Flexible Electronics.

A third crucial item for flexible electronic systems is memory, both non-volatile and volatile. We have demonstrated an 8kb laser programmable memory and the first readout of non-volatile memory cells.

During the project, we also explored a different field, namely security. This will be a key topic for edge computing and patches. A cryptographic chip is implemented with a large number of transistors. Therefore, we have selected a cryptochip which executes a lightweight algorithm and realized the world-first security chip on flex. This was well received at the CHES conference in 2019 and won the best paper award.

Finally, in the technology of PragmatIC, we are pioneering to setup a multi-project-wafer foundry model, which will be very important for society. I am considering at this moment to write an ERC POC project specifically on this topic. With the PragmatIC downscaled IGZO technology, we have demonstrated the fastest flexible microprocessor circuit which is published in ISSCC 2022. We also demonstrated the real time operation of this chip by programming a Snake game and playing it live on the demonstration session of ISSCC conference. This received lots of attention and got public on the Belgian TV.
The key figures of merit for this project can be categorized in 3 categories: power consumption, level of integration and downscaling. The description of progress beyond the state of the art will be discussed with those categories.

For downscaling, we have been downscaling to 1.5µm targeting the NFC application. The channel lengths are not state-of-the-art, however, the resulting chip based on this technology resulted in state-of-the-art performance. We have realized 2.4ns gate delays, and a power consumption of a full NFC chip employing these transistors of only 7.5mW which is state-of-the-art today. These gate delays are also still state-of-the-art for IGZO circuits on flexible substrates.

To take the scaling to the next level in the second half of the project, we have collaborated with a foundry and implemented circuits with the state-of-the-art channel lengths of 800nm for IGZO transistors on flexible substrate. This yielded fast, robust, and complex digital circuits on flexible substrate and some high-level conference publications. These channel lengths are state-of-the-art for flexible circuits based on IGZO today.

The power consumption of individual logic gates has been improved by introducing crossover logic and by elaborating different logic styles in one chip. This has contributed to the state-of-the-art 7.5mW metal-oxide based NFC tag, but also contributed to the 160nW power consumption of a full code generator chip on flex for capacitive identification purposes.

The final mission of this project was to enable VLSI circuits on flex by reducing power consumption at design and technology level. Integration density wise, we have demonstrated state-of-the-art laser programmable ROM memory size of 8kb, which was designed generic and turns out be easily upscalable. Our security chip employs 4044 n-TFTs.
In parallel with the pre-defined targets of the project, we have realized a complex digital circuit which is the flexible version of 6502 microprocessor, and it employs 16392 thin-film transistors. In parallel with logic architecture study and system level optimizations, we have adapted the digital design flow for unipolar TFT technologies specifically. While it is still possible to realize even larger circuits with this technology (and was demonstrated by ARM and PragmatIC independently), it might be an overkill for low power IoT applications which needs to low power.