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Enabling flexible integrated circuits and applications

Periodic Reporting for period 3 - FLICs (Enabling flexible integrated circuits and applications)

Reporting period: 2020-01-01 to 2021-06-30

The goal of this FLICs proposal is to develop disruptive technology and ground-breaking design innovations with amorphous oxide TFTs on plastic substrates, targeting large scale or very large scale flexible integrated circuits with unprecedented characteristics in terms of power consumption, supply voltage and operating speed, for applications in IoT and wearable healthcare sensor patches.
We introduce a new logic style, “quasi-CMOS”, which is based on unipolar, oxide dual-gate thin-film transistors. This logic style will drastically decrease the power consumption of unipolar logic gates in a novel way by taking advantage of dynamic backgate driving and of the transistor’s unique low off-state leakage current, without compromising on switching speed. Throughout the project, we will investigate on different logic styles which take advantage of the transistor’s unique properties.
On another angle, we also introduce downscaling of the transistor’s dimensions, while remaining compatible with upscaling to large-area manufacturing platforms and as such introduce Moore’s law on flex. This will enable to improve the energy-delay product significantly and therefore pave the way to novel application areas.
Finally, we will investigate novel ultralow-power design techniques on system-level, while exploiting the quasi-CMOS logic gates. Combining all these low-power and improved energy-delay options would pave the way for the realization of unprecedented flexible VLSI circuits. The application areas that are envisioned in this project are flexible IoT communication chip, metal-oxide based wearable healthcare patches and processor cores.
In this period, we have been very active on the logic style analysis with a strong emphasis on low-power unipolar logic gates. We have been able to reduce the inherently present static leakage current of inverters. The result of this route has been recently published as crossover logic, yielding a fivefold reduction in power consumption. Besides this novel circuit architecture, we have improved the power consumption of regular circuit topologies necessary to enable capacitive readout circuits. The aforementioned circuit consumed less than 160nW.
Introducing the Moore’s law on flex roadmap, we have pursuing downscaling until 1.5µm. The target in this ERC project is to move towards VLSI circuits on flex, which required a stable downscaled transistor. As a result, the 1.5µm transistors embedded in a ring oscillator yielded the fastest reported metal-oxide based circuit exhibiting a stage delay of only 2.4ns on flexible substrates.
One of the routes in this project is to innovate at system level design, enabling new applications for this technology. The first real application that was realized is the world-first IGZO-based NFC tag due to a few key achievements within this project: (1) downscaling of the self-aligned technology yielding NFC-compatible operating voltages and inverter delays enabling direct clock recovery; (2) introducing low-power design technique like logic style partitioning and optimization for speed, robustness and low power. The NFC tag was well-received by the TFT community, leading to an ISSCC paper, an invited perspective article in Nature Electronics and several invited talks at conferences.
The second application window that was envisioned are healthcare patches and sensor-node IoT devices. In this field, the team has worked on analog-to-digital converters as key circuit blocks for such systems, which are published in several papers.
A third crucial item for flexible electronic systems is memory, both non-volatile and volatile. We have demonstrated an 8kb laser programmable memory and the first readout of non-volatile memory cells.
Security will be a key topic for edge computing and patches. A cryptographic chip is implemented with a large number of transistors. Therefore, we have selected a cryptochip which executes a lightweight algorithm and realized the world-first security chip on flex. This was well received at the CHES conference in 2019 and won the best paper award.
The key figures of merit for this project can be categorized in 3 categories: power consumption, level of integration and downscaling. The description of progress beyond the state of the art will be discussed with those categories.

For downscaling, we have been downscaling to 1.5µm targeting the NFC application. The channel lengths are not state-of-the-art, however, the resulting chip based on this technology resulted in state-of-the-art performance. We have realized 2.4ns gate delays, and a power consumption of a full NFC chip employing these transistors of only 7.5mW which is state-of-the-art today. Regarding downscaling, we target submicron channel lengths by the end of the project, with tens of ps gate delays.

The power consumption of individual logic gates has been improved by introducing crossover logic and by elaborating different logic styles in one chip. This has contributed to the state-of-the-art 7.5mW metal-oxide based NFC tag, but also contributed to the 160nW power consumption of a full code generator chip on flex for capacitive identification purposes. The final target of this ERC project is to decrease the power consumption below 1nW.

The final mission of this project is to enable VLSI circuits on flex by reducing power consumption at design and technology level. Integration density wise, we have demonstrated state-of-the-art laser programmable ROM memory size of 8kb, which was designed generic and turns out be easily unscalable. Our security chip employs 4044 n-TFTs. The final target in the project is to realize flexible metal-oxide based chips employing >10000 nTFTs.