The aim of ADEQUAT is to develop the basic process steps and process modules for future 0.35 micron and 0.25 micron CMOS technologies for logic applications.
The project will concentrate on the early development and demonstration of the feasibility of the individual process modules for 0.25 micron CMOS technology. In the first phase, this effort will be carried out in the framework of 0.35 micron lithography, and the feasibility of major process steps will be demonstrated by the fourth quarter of the first year of the project. This will lead to the optimisation and stabilisation of advanced 0.35 micron modules in a 0.5 micron CMOS technology by the end of the project. The possible benefits resulting from the new modules (eg in terms of performance enhancement, process margin or process control improvement or better productivity) will be analysed and reported, which will lead to individual decisions on the process module transfer by the manufacturers.
In parallel, work will be done on modelling and understanding deep sub-micron failure mechanisms and on advanced local analysis and 2-D profiling in relation to advanced process and device modelling.
A work-plan for a second phase will propose the extension into the 0.25 micron regime, leading to the stabilisation of 0.25 micron modules in a 0.35 micron environment and work on 0.35 microns back-end modules.
The Joint Logic Project (JLP, 7363), in which all the major European IC manufacturers have joined forces, will be the main beneficiary of ADEQUAT's results. Furthermore, all the industrial partners will transfer know-how and exploit ADEQUAT modules in their pilot line environment for the development of CMOS logic production processes.
For further information, see project 8002, which describes in more detail the first and second phases of ADEQUAT.
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