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Deep sub-micron microprocessor for spAce rad-Hard appLIcation Asic

Periodic Reporting for period 3 - DAHLIA (Deep sub-micron microprocessor for spAce rad-Hard appLIcation Asic)

Reporting period: 2020-05-01 to 2021-06-30

DAHLIA met its target to develop an innovative real-time System-on-Chip for space applications where mixed-criticalities between co-running applications are guaranteed and where resources are allocated in time and space to the running applications. Overall, the main novelties of the project are:
1. European None Dependence, achieved through the use of European semiconductor technology and European IP technologies. The Consortium is made of key technology industrial partners.
2. Combination of a Very High Performance microprocessor, achieving state-of-the-art real-time performances based on European 28nm FDSOI with multicore ARM processor for real time applications and a very large embedded FPGA device for flexibility support. The chip was designed for the complete platform with 28 nm FDSOI technology offering outstanding intrinsic radiation robustness.
3. A common definition of the SoC between the main actors of the European Space Industry, with the largest scope of space applications, optimised development costs and increased competitiveness of the European Space Industry. DAHLIA System-on-Chip contains the following main features:
• 4 x ARM Cortex-R52 with Debug & Trace
• SoC Services such as Clock & Reset management, Timers & Watchdog, Temperature & Voltage sensors, Secure Boot
• CCSDS On Board Time
• On-Chip Memories all protected by ECC
• External Memory interface supporting Non Volatile (Flash) and Volatile (DDR) memories with ECC
• Multi-channel DMA controller
• CCSDS TM & TC
• GNSS
• Wide range of communication links: SpW, 1553, UART, CAN, SPI, HSSL…
• Embedded FPGA for flexibility
4. Real-time support with the new ARM Cortex-R52 processors, to cope with the mixed-criticalities of the co-running applications. The Cortex-R Series have been developed by ARM to offer performance for real-time applications. Within the Cortex-R family, the Cortex-R52 represents ARM’s most advanced processor in term of performances and safety.
5. The usage of the naturally immune to latchup STMicroelectronics 28nm FDSOI technology, to implement the High performance Microprocessor

DAHLIA developed a Very High Performance microprocessor System on Chip (SoC) based on STMicroelectonics European 28nm FDSOI technology with multi-core ARM processors for real-time applications, eFPGA for flexibility and key European IPs, enabling faster and cost-efficient development of products for multiple space application domains.
The performance is 20 to 40 times the performance of the existing SoC for space. This performance level, combined with a large set of integrated peripherals including dedicated on-chip functions for GNSS, TM and TC support, will enable key space applications to be executed within the same microprocessor significantly reducing cost and mass and boosting competitiveness of future European space equipments.
With the highest cumulative number of European satellites and electronics equipments successfully operating in orbit, Airbus Defense and Space and Thales Alenia Space represent together the indisputable best positioned companies in Europe to ensure the maximum relevance of the DAHLIA SoC for its future use by the whole European Space community.

Beyond Space applications, the adoption of the ARM processor will enable the convergence with terrestrial applications benefiting from the strong ARM ecosystem while the new SoC is ensuring European strategic non dependence for the most critical component on board.

As a conclusion, Dahlia has allowed to improve the availability of building blocks that will benefit any future Integrated Avionics based on NG-Ultra, with the coverage of both GNSS and OBC use cases completed by Software benchmarks.
The first reporting period was dedicated to the project set-up and the beginning of the design phase both at IP and SoC top level stages:
1. SoC requirements have been defined and synthetized by Thales in a single document: deliverable “D4.1 – DAHLIA SoC Requirements Specification Document”.
2. The architecture of the SoC has been defined by the consortium with Airbus as a leader. The architecture definition has been done in two steps:
a. A high level architecture description: deliverable D5.1 – Preliminary SoC Architecture Description
b. A detailed architecture description: deliverable D5.2 - Final SoC Architecture Description
During this definition phase a particular focus has been put by NanoXplore on the FPGA bitstream security.
3. STMicroelectronics gave access to the consortium to its ARM IP licenses and to the 28FDSOI design environment.
4. All of the IPs that are mapped in ASIC gates were fully released. WP6/7 & 8. Plus the additional NX Ips
5. Final top level RTL, synthesis were released according WP9&10
6. The validation strategy was completely reviewed and improved by ISD. Delivered D12.1
7. The First samples manufacturing, to feed WP12 validation, were followed by STM, as per requested in WP11 and traced in D11.2.
8. The Dahlia SOC validation, in addition with the two users validations were compelted by ISD, ADS and TAS, up to the validation reports (deliverables D12.2 D12.3 and S12.4)
9. The DAHLIA project were presented in 22 conferences and 3 workshops. The details of the conferences are available on DAHLIA web site at http://dahlia-h2020.eu
Dahlia project delivered the expected Dahlia SOC to NG-Ultra and validated its implementation as per the effort done in WP12.
From now, the success of the SOC Dahlia in NG-Ultra will rely on the quality of its NG-Ultra ecosystem, hardware and software, and so creating and improving the building blocks that could be available for this European component is a key step for a better European non-dependence. Moreover, it is an enabler for a faster time-to-market development of future applications based on the NG-Ultra.
Based on these improvements and based on the outputs from Dahlia validation WP12, at the end of the Dahlia project, the performance is still expected to be 20 to 40 times the performance of the existing SoC for space and more than 2 times the performance of the future quad core LEON4 chip. This performance level, combined with a large set of integrated peripherals including dedicated on-chip functions for GNSS, TM and TC support, will enable key space applications to be executed within the same microprocessor significantly reducing cost and mass and boosting competitiveness of future European space equipment.
Considering the Cortex-R52 performance and the frequency achieved with the 28 nm technology, we can estimate the overall DAHLIA performance beyond 4000 DMIPS in future final application
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