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Universal microwave photonics programmable processor for seamlessly interfacing wireless and optical ICT systems

Periodic Reporting for period 3 - UMWP-CHIP (Universal microwave photonics programmable processor for seamlessly interfacing wireless and optical ICT systems)

Reporting period: 2020-07-01 to 2021-12-31

For ICT systems to cope with rapidly increasing traffic growth rates there is a need for a flexible, scalable and future-proof solution for seamlessly interfacing the wireless and photonic segments of communication networks. In addition, emerging paradigms such as 5G/6G communications,
Internet of Things (IoT), autonomous driving, wireless body and personal area networks (WB/PANs) and high-resolution sensing are expected to exacerbate this pressure even further. The requirements demanded by most of these scenarios call for novel technology developments in both the physical layer and the network architectures and this is the main issue being addressed by the project.
RF or Microwave photonics (MWP) is a technology that brings together the worlds of radiofrequency (RF) engineering and optoelectronics interfacing these highly dissimilar media. It is the best positioned technology to provide a flexible, adaptive and future proof physical layer with unrivalled characteristics as it enables the realization of key functionalities in microwave systems, which are either complex or even not directly possible within the radiofrequency (RF) domain. However, MWP is currently limited by the high-cost, bulky, complex and power consuming nature of its systems. The major challenge in MWP research is therefore to reduce their cost, size, weight and power consumption (SWaP) while providing flexible and reconfigurable operation. Achieving this will constitute a ground-breaking milestone with dramatic scientific, societal and economic impacts.
UMWPCHIP project goes beyond the current state of the art by pioneering the novel field of Integrated Microwave Photonics (IMWP), which targets the incorporation of MWP components/subsystems in monolithic or hybrid photonic circuits. The activity in IMWP to date has almost exclusively focused on the so-called Application Specific Photonic Integrated Circuit (ASPIC) paradigm, where a particular circuit and chip configuration is designed to optimally perform a particular MWP functionality. As a result, there are almost as many technologies as applications and, due to this considerable fragmentation, the market for many of these application-specific technologies is too small to justify their further development into cost-effective industrial mass-volume manufacturing processes.
The groundbreaking nature of UMWPCHIP resides in its radically different technical approach: rather than following the ASPIC paradigm, the project aims to develop a universal MWP signal processor architecture based on a photonic waveguide mesh that: a) can be integrated on a chip, b) features parallel input/output operation and c) is capable of performing all the main functionalities by suitable software programming of its control signals. In this sense, UMWPCHIP is inspired by the similar flexibility principles of Digital Signal Processors (DSPs) and Field Programmable Gate Arrays (FPGAs) in electronics, where a common hardware is shared by multiple functionalities through a software-defined approach (or programmability), this will allow for significant cost reduction in the hardware fabrication. Such a universal processor will overcome the former limitations and enable further flexibility and SWaP reductions as compared to the current ASPIC-based paradigm.
The overall objective of UMWPCHIP is the design, implementation and validation of a universal integrated microwave photonics programmable signal processor. This processor, capable of performing the most important MWP functionalities (filtering, beamsteering, arbitrary waveform generation, frequency up/down conversion, instantaneous frequency measurement and high-purity optoelectronic oscillation) featuring unique broadband and performance metrics, paving the way towards the flexible, scalable and future-proof interfacing between fiber and wireless segments of ICT systems supporting an ever increasing number of ICT systems and applications and emerging fields.

Research activities within UMWPCHIP are structured into three workpackages that target specific objectives. The first one deals with main theoretical and design aspects related to the top-level architecture of the MWP signal processor and its optical core, addressing as well the optimization and the drafting of specifications to be employed in its fabrication, assembly, testing and experimental demonstrations. The second, takes charge of the chip mask design, fabrication, packaging and testing of the processor and finally, the third wordpackage deals with the experimental demonstration and validation of the processor for a set of application functionalities. The work carried so far during this period has been mainly in WP1 and WP2 although some preliminary activities in WP3 have also been started.

Most of the activity carried during this period is connected to the top-level architecture of the MWP signal processor. We have analyzed several alternatives for the implementation of the waveguide mesh integrated core and found the hexagonal to be the most efficient. The multifunctional operation of this architecture has been both theoretically and experimentally demonstrated and we have derived novel analytical methods for its modeling (these are unique in many aspects and we have proceed to patent them). We have we have reported the different alternatives leading to its integration into the overall processor. Among these, we would like to emphasize the Field Programmable Photonics Gate Array (FPPGA) option, whereby the waveguide mesh is integrated with a set of input/output ports and several high-performance blocks (HBBs) that surround it. HPBs can include sources, modulators, detectors or specialized photonic circuits. The FPPGA concept is a completely original derivation of this project and we believe it to be a disruptive concept whose application goes beyond the MWP field. This is why we have selected it for patent application and as a transferrable technology that was the subject of an ERC-PoC application that has been successfully evaluated and funded. The work on WP1 has also included the end-to-end modeling of the full processor under passive operation and we are close to finish the overall modeling for the case where the processor core includes active photonic components for power loss compensation. We have developed methods for the monitoring, control, programming and optimization of the processor core. These methods are essential as well for studying the scalability of the processor. Extension of these from the core to the overall processor will be addressed after the completion of the end-to-end modeling incorporating active elements. Further to the main work carried in modeling we have drafted the high-level specifications required for the first chip mask design stage in the fabrication of the optical core.

The work related to the chip mask design, fabrication, packaging and testing of the processor has been carried in several parallel steps. An initial period of activity has been devoted to contact the relevant foundries to be considered for the passive (CEA-LETI, IMEC, Cornerstone and IMS) and active (HHI, Smart Photonics) chip fabrication as well as the relevant packagers Tyndall and Ficontech). As a result, CEA-LETI foundry was selected for the first run of the silicon photonics waveguide mesh core, while IMF will be in charge of the dedicated run on the overall processor. In parallel, a new lab was assembled from scratch, including the purchase and the installation of three different measurement setups for Silicon, InP and fiber-arrayed photonic chips. These setups are now ready for use in the testing stage of this project. PhD students and Postdocs have received several training courses on integrated optics design and testing. In-house they have carried training activities in test and characterization using simple SOI and InP chips which have been useful as well in setting up the computer-controlled automatization processes that will be required at later stages of the project.

Upon completion of the design phase for the first fabrication run in WP1 we produced the layout and mask for the first fabrication run of the waveguide mesh core. This design includes 10 hexagonal cells and incorporates modulators and detectors in the same chip. The files were sent to CEA-LETI for fabrication, which was completed in December 2019. Unfortunately an overall delay of six months has been produced so the chips are expected by the end of may 2020. Chip testing and characterization will be subsequently carried. In parallel, the design of the overall processor chip has also been started. This includes, in addition to the photonic waveguide mesh the design and fabrication of the electronic and RF driving circuits and their integration in a printed circuit board (PCB).
Finally, a preliminary activity in WP3 has started that is focused on providing the specifications and requirements for the measurement protocols of the full processor in several MWP application scenarios. Required additional RF components have been identified and procured. Required additional RF instrumentation and acquired thanks to a 1M€ grant awarded to the principal researcher by the Valencian Government.
The research activities carried out in the first two and a half years of UMWPCHIP have led to the following main advances beyond the state of the art:

• First multifunctional integrated hexagonal waveguide mesh in Silicon on Insulator technology capable of experimentally demonstrating over 30 different functionalities, including programmable Finite (FIR) and infinite impulse response (IIR) filtering, true time delaying, tunable beamforming by phase shifting and multiport interferometer emulation.
• First proposal and experimental demonstration of dual drive tunable directional couplers as elementary building blocks capable of independent setting of amplitude and phase and their integration into the first-ever reported triangular waveguide mesh fabricated in Silicon Nitride.
• First-ever derivation and patenting of an analytic method to compute the scattering matrix of a two-dimensional photonic integrated device with full coupling in the X and Y axis. The fact that the method is analytic and not numerical allows a high-speed calculation time of the transfer function of multiport 2D devices, which is essential for further monitoring and control tasks.
• The proposal experimental demonstration and patenting of a new device, the Field Programmable Photonic Gate Array (FPPGA), which can be applied to MWP field but also in other areas such as quantum information processing, artificial intelligence and sensing.
• The first-ever development and experimental demonstration of multipurpose optimization techniques for the monitoring, control and resource setting and programming of large-scale waveguide mesh circuits. The methods can rely either on prior measurement or calibration of the hardware elements or run without prior knowledge of the processor settings. These techniques combine the fast analytic scattering matrix method and refined population and machine learning optimization algorithms.

In the remaining second and a half years of UMWPCHIP, we expect the following research results and progress beyond the state of the art:

• Complete end-to-end models for the design of FPPGA devices incorporating photonic, electronic and RF elements.
• Complete design and fabrication of a FPPGA featuring a silicon on insulator core with over 20 hexagonal cells and over 200 tuning elements, a complete electronics monitoring and driving unit and Fiber optics and RF input/output ports.
• The demonstration of the above FPPGA device in several different MWP functionalities from the following list: filtering, beamforming, arbitrary waveform generation, optoelectronic oscillator, mixing, and true time delaying and performance operation complying with the RF metrics limited by state of the art integrated components.
• The demonstration of the same FPPGA device in other fields of applications, including the emulation of programmable multiport interferometers and the implementation of two or more simultaneous functionalities in the same hardware.
• The demonstration of the self-healing and autorouting capabilities of the FPPGA device.