Periodic Reporting for period 1 - SILICON (Self-Injection-Locked Integrated Analog-to-Digital Converter)
Reporting period: 2017-04-01 to 2019-03-31
The exploited project fits within the broad field of the Internet of Things (IoT) and, more specifically, within the sensing elements of wireless sensor networks (WSNs), referred to as IoT nodes. IoT nodes must comply to ever increasing level of power efficiency so as to maximize the battery lifetime. Such primary requirement can be achieved through innovative circuit architectures, able to operate at an ultra-low voltage (ULV) supply, which also entails the great benefit of allowing to supply the circuit directly from the output voltage of energy harvesters (e.g. solar cells) without the need of a boost DC-DC voltage converter, which further deteriorates the IoT node overall power efficiency. Therefore, the design of the integrated circuits (ICs) within IoT wireless sensor nodes can only target a superior power efficiency by means of ultra-low-power (ULP) and ULV design techniques and by adopting nanoscale CMOS technology to enable inexpensive large scale integration. It is indeed mandatory to emphasize that CMOS is the primary enabling technology of the ongoing IoT revolution, given the huge number of IoT devices. As a consequence, the analog section of an IoT SoC must adopt the mainstream CMOS technology (good for digital logic) while meeting stringent project specifications (e.g. noise, gain). Under such constraints, it is therefore evident how conventional analog-intensive circuit architectures for implementing the sensing front-end and the RF TRXs are unsuitable in the context of an IoT node.
The exploited project focused on the sensing front-end readout chain of an IoT node and, in particular, on the analog-to-digital converter (ADC). ADCs are fundamental circuits in any receiver chain (both sensors and RF front-ends), which represent the interface between the analog domain and the digital world and, as any other block of such chain, their power efficiency must be maximized. Having outline the voltage-controlled-oscillator- (VCO-) ADC architecture as the most suitable candidate for digitally-intensive ULP and ULV CMOS SoCs, the main focus of the exploited action was to explore solutions to inherently solve the main impairment of this topology of ADCs, i.e. the intrinsic nonlinearity of the VCO transfer curve. Therefore, the main targeted objectives of this action were: performing a thorough theoretical investigation and feasibility study on the circuit architecture proposed in Annex 1 of this MSCA IF grant proposal; validating experimentally the outcome of the first feasibility study by measuring the first IC prototype, thus providing guidelines for a second design iteration; designing the second IC prototype and experimental validating it. The researcher refers to the said objectives as the initial and principal project goals, but he deems worth mentioning that additional activities have been carried out, all of which targeting the design of ULP ADCs for IoT applications. Indeed, the researcher has been involved in the design of a digitally-intensive ULP level-crossing sampling ADC for biomedical and IoT applications, a charge-pump-based time-mode ULP and ULV ADC, a mismatch-calibrated SAR ADC and a linearity calibrated SAR time-to-digital converter (TDC).
The exploited action equipped the researcher with extremely valuable skills in the field of low-power time-mode analog-to-digital conversion, both of theoretical, methodological and technical nature, designing in nanoscale CMOS technologies. The main research activity has outlined that the principle of self-injection locking, exploited so as to mitigate the nonlinear tuning curve of the VCO-based ADC, proves to be insufficiently effective, although beneficial, in completely addressing the inherent nonlinearity impairments of VCO-based ADC. However, this first phase of the action paved the way towards the second VCO-based ADC design, whose development demonstrated the suitability of an alternative linearization technique, which instead proved to be perfectly effective and allows to operate the VCO-based ADC at open-loop. In addition, such technique, which leverage on a mixed voltage-current mode tuning scheme based on a programmable resistive-network, further allows the ADC to be operated at the ultra-low supply voltage of 0.2V thus considerably decreasing its power consumption and significantly improving the overall ADC power efficiency.
The exploited project focused on the sensing front-end readout chain of an IoT node and, in particular, on the analog-to-digital converter (ADC). ADCs are fundamental circuits in any receiver chain (both sensors and RF front-ends), which represent the interface between the analog domain and the digital world and, as any other block of such chain, their power efficiency must be maximized. Having outline the voltage-controlled-oscillator- (VCO-) ADC architecture as the most suitable candidate for digitally-intensive ULP and ULV CMOS SoCs, the main focus of the exploited action was to explore solutions to inherently solve the main impairment of this topology of ADCs, i.e. the intrinsic nonlinearity of the VCO transfer curve. Therefore, the main targeted objectives of this action were: performing a thorough theoretical investigation and feasibility study on the circuit architecture proposed in Annex 1 of this MSCA IF grant proposal; validating experimentally the outcome of the first feasibility study by measuring the first IC prototype, thus providing guidelines for a second design iteration; designing the second IC prototype and experimental validating it. The researcher refers to the said objectives as the initial and principal project goals, but he deems worth mentioning that additional activities have been carried out, all of which targeting the design of ULP ADCs for IoT applications. Indeed, the researcher has been involved in the design of a digitally-intensive ULP level-crossing sampling ADC for biomedical and IoT applications, a charge-pump-based time-mode ULP and ULV ADC, a mismatch-calibrated SAR ADC and a linearity calibrated SAR time-to-digital converter (TDC).
The exploited action equipped the researcher with extremely valuable skills in the field of low-power time-mode analog-to-digital conversion, both of theoretical, methodological and technical nature, designing in nanoscale CMOS technologies. The main research activity has outlined that the principle of self-injection locking, exploited so as to mitigate the nonlinear tuning curve of the VCO-based ADC, proves to be insufficiently effective, although beneficial, in completely addressing the inherent nonlinearity impairments of VCO-based ADC. However, this first phase of the action paved the way towards the second VCO-based ADC design, whose development demonstrated the suitability of an alternative linearization technique, which instead proved to be perfectly effective and allows to operate the VCO-based ADC at open-loop. In addition, such technique, which leverage on a mixed voltage-current mode tuning scheme based on a programmable resistive-network, further allows the ADC to be operated at the ultra-low supply voltage of 0.2V thus considerably decreasing its power consumption and significantly improving the overall ADC power efficiency.
The work performed can be divided into three distinguished phases: 1) experimental validation of the first circuit prototype, 2) second design iteration and 3) experimental validation of the second prototype. The first phase validated the idea implemented in the first design, thus verifying the validity of all of the assumptions made in the feasibility study presented in the grant proposal of this project. The outcomes from this first phase represented the starting point of the second phase, whose focus was to refine and explore alternative linearization techniques suitable for operating the VCO-based ADC at open loop and to moreover extend the applications scenario to ultra-low-voltage applications. The third phase dealt instead with the electrical measurements of the second IC prototype, fabricated in the low-power flavor of a standard 28nm bulk CMOS technology.
Among the aforementioned three phases of the project, only the third and last one produced relevant results of scientific interest for the wider microelectronics community, whereas the first two served the fundamental purpose of building the necessary knowledge to bring the project towards the good level of maturity achieved so far. Considering the main project activities (i.e. those related to the above-mentioned three phases), the outcome of this action is an ultra-low power open-loop VCO-based ADC operating under a 0.2V nominal supply voltage and dissipating a power consumption of 7 uW at a sampling rate of 30 MS/s, while achieving at 11-bit effective number of bits (ENOB), thus resulting in a best-of-class power efficiency among deep subthreshold and near threshold ADCs.
The achieved results have been disseminated in three ways: in 2017 through a conference (IEEE International Conference on Event-Based Control, Communication and Signal Processing) and a workshop at the AGH University of Technology in Krakow, while in early 2019 through a journal paper (IEEE Solid-State Circuits Letters).
Among the aforementioned three phases of the project, only the third and last one produced relevant results of scientific interest for the wider microelectronics community, whereas the first two served the fundamental purpose of building the necessary knowledge to bring the project towards the good level of maturity achieved so far. Considering the main project activities (i.e. those related to the above-mentioned three phases), the outcome of this action is an ultra-low power open-loop VCO-based ADC operating under a 0.2V nominal supply voltage and dissipating a power consumption of 7 uW at a sampling rate of 30 MS/s, while achieving at 11-bit effective number of bits (ENOB), thus resulting in a best-of-class power efficiency among deep subthreshold and near threshold ADCs.
The achieved results have been disseminated in three ways: in 2017 through a conference (IEEE International Conference on Event-Based Control, Communication and Signal Processing) and a workshop at the AGH University of Technology in Krakow, while in early 2019 through a journal paper (IEEE Solid-State Circuits Letters).
The exploited action significantly progressed beyond the state-of-the-art in VCO-based ADCs. Focusing on IoT applications, the proposed design outperforms all of the previously published VCO-based ADCs as for power efficiency, as well as sub- and near-threshold ADCs with similar bandwidth, while achieving an ENOB higher then 10-bit at open-loop and against 20% supply voltage variations and on multiple measured ICs, thus demonstrating robustness versus Process and Voltage variations.
The results achieved by this action provide strong evidence that the VCO-based ADCs are among the preferable candidates for ULP and ULV nanoscale CMOS SoCs, thus particularly suitable for future 7 and 5 nm CMOS process nodes.
The results achieved by this action provide strong evidence that the VCO-based ADCs are among the preferable candidates for ULP and ULV nanoscale CMOS SoCs, thus particularly suitable for future 7 and 5 nm CMOS process nodes.