Periodic Reporting for period 3 - e-See (Single electron detection in Transmission Electron Microscopy)
Reporting period: 2021-10-01 to 2023-03-31
The e-See project aims at studying electric phenomena (charges, electric fields, electrostatic potential) in semiconducting nanostructures in a quantitative way, with the ultimate goal of detecting a single deterministically controlled charge with nm scale spatial resolution using electrical in-situ transmission electron microscopy (TEM). Many devices we use in everyday life work because of their electrical properties: for example, our phones and laptops are built with a multitude of transistors. The industry aims to make these transistors smaller, faster and reduce their energy consumption.
This is related to the challenge addressed in this project that nominally identical transistors can have variable performance at short channel length. In a state-of-the-art silicon transistor, we find a channel between source and drain, underneath a gate. Source and drain are made highly conductive using ion implantation, but this can also lead to one or few dopant atoms in the channel, generating a high off current and increasing the power consumption. This variability issue, coming from stray dopants, impacts semiconductor industry today.
Regarding variability, a single atom can create a level in the channel. At room temperature, current flows very fast from source to drain trough the available levels in the channel, and electrons are therefore delocalized and are very difficult to detect. However, if we lower the temperature of the system, we can trap one or few charges on the available levels in the channel, in a Coulomb blockade experiment.
Coulomb blockade is currently used in low temperature transport experiments. However, no direct spatial resolution is obtained in these experiments. This is the novel characterization method we develop.
We aim to combine TEM based techniques such as electron holography and differential phase contrast with low temperature experiments to perform a Coulomb blockade experiment and using the contacts on the transistor for in-situ biasing, providing electrical control of the trapped charge(s).
Adjusting chemical potential of source drain and gate we can put zero charges in the channel, and make an image. Then we adjust the chemical potential to put a single or discrete number of charges in the channel, and make an image. Taking the difference of both images removes all contrast but the influence of the change in charge.
The target is to electrically control and spatially locate a single or discrete number of trapped charges in the device volume with nm or even atomic spatial resolution.
Apart from transistors, this method can be applied to many other systems.
We are developing a cooled electrical biasing TEM sample holder.
We are working on sample preparation using an approach based on nitride membranes and lithography, that we have been pioneering since 2010.
And finally aim to combine TEM and transport experiments.
It should be realized that the channel of a transistor is very similar to a nanowire, a wire like structure with diameter in the order of tens of nm, therefore we have started using semi conducting nanowires as a model system.
Once proof of principle is obtained, we will use state of the art transistors fabricated by our collaborators and render them electron transparent using a backside etching approach.
This project may create a paradigm shift in transistor characterization, both in-line due to the improved sample fabrication using backside etching that will allow massively parallel sample fabrication on the wafer scale, and off line due to this novel method. Finally, the project may potentially improve transistors, but this can be outside the timeframe of this project.
This is related to the challenge addressed in this project that nominally identical transistors can have variable performance at short channel length. In a state-of-the-art silicon transistor, we find a channel between source and drain, underneath a gate. Source and drain are made highly conductive using ion implantation, but this can also lead to one or few dopant atoms in the channel, generating a high off current and increasing the power consumption. This variability issue, coming from stray dopants, impacts semiconductor industry today.
Regarding variability, a single atom can create a level in the channel. At room temperature, current flows very fast from source to drain trough the available levels in the channel, and electrons are therefore delocalized and are very difficult to detect. However, if we lower the temperature of the system, we can trap one or few charges on the available levels in the channel, in a Coulomb blockade experiment.
Coulomb blockade is currently used in low temperature transport experiments. However, no direct spatial resolution is obtained in these experiments. This is the novel characterization method we develop.
We aim to combine TEM based techniques such as electron holography and differential phase contrast with low temperature experiments to perform a Coulomb blockade experiment and using the contacts on the transistor for in-situ biasing, providing electrical control of the trapped charge(s).
Adjusting chemical potential of source drain and gate we can put zero charges in the channel, and make an image. Then we adjust the chemical potential to put a single or discrete number of charges in the channel, and make an image. Taking the difference of both images removes all contrast but the influence of the change in charge.
The target is to electrically control and spatially locate a single or discrete number of trapped charges in the device volume with nm or even atomic spatial resolution.
Apart from transistors, this method can be applied to many other systems.
We are developing a cooled electrical biasing TEM sample holder.
We are working on sample preparation using an approach based on nitride membranes and lithography, that we have been pioneering since 2010.
And finally aim to combine TEM and transport experiments.
It should be realized that the channel of a transistor is very similar to a nanowire, a wire like structure with diameter in the order of tens of nm, therefore we have started using semi conducting nanowires as a model system.
Once proof of principle is obtained, we will use state of the art transistors fabricated by our collaborators and render them electron transparent using a backside etching approach.
This project may create a paradigm shift in transistor characterization, both in-line due to the improved sample fabrication using backside etching that will allow massively parallel sample fabrication on the wafer scale, and off line due to this novel method. Finally, the project may potentially improve transistors, but this can be outside the timeframe of this project.
The project has three Work Packages:
• WP1: developing a low temperature in-situ electrical Transmission Electron Microscopy (TEM) holder
• WP2: sample fabrication for electrical in-situ TEM
• WP3: low temperature and transport experiments
WP1
Three prototypes have been made for the cryogenic liquid He electrical TEM sample holder. The first prototypes combined relatively high heat losses and a high weight of the He dewar. Therefore, a third prototype was developed where the conception of the He dewar was changed, improving both it’s thermal insulation and weight.
The third prototype is now ready and many cryogenic tests have been performed on this prototype, improving it step by step. 4K can now be reached during 17 min.
In WP2 we have advanced on the membrane fabrication, making membrane-chips compatible with different TEM holders and therefore TEM installations. We have acquired holders to perform a local back side etching, to render devices transparent by a backside etching process, while protecting the device side from the etching solution. We have published a review of our fabrication protocol and studies that were enabled by this technology, article 8.
At present, the most challenging aspect of this project appears to be the effect of the electron beam on our sample, especially for such delicate phenomena like Coulomb Blockade.
Therefore, we have started to work at samples containing many charges, to see if their properties can be reliably measured by in-situ TEM at room temperature. This will already constitute a major advancement in material characterization.
We focus on the following topics for WP3:
p-n junctions in NWs.
This is a model system for charge related phenomena, that is also interesting on its own accord, for example with respect to NW solar cells.
Al contact on Ge and SiGe NWs.
We have studied the exchange reaction between Al metal contacts on Ge and SiGe NWs, and observed that the Ge from the NW is replaced by Al. This is an interesting system for transport because the interfaces are very well defined and we can make a Ge QD of deterministic size using in-situ TEM (article 1).
InAs/InP NW heterostructure. We aim to use this system as a model system for proof of principle experiments of Coulomb blockade in the TEM.
GaN/AlN NW quantum dots.
We have studied the correlation of electro-optical properties with structure in GaN/AlN NW’s. Moreover, in-situ biasing combined with micro photoluminescence (μPL) allowed modifying the emission energy of a single GaN QD in a GaN NW (article 5). We have performed in-situ experiments on these samples to measure the internal fields and their change with applied bias using TEM techniques.
GaAs spontaneous polarization studies by holography.
To allow measuring a single charge, we will need to be able to measure very small electric fields. As a model system of very small internal electric fields, we have performed experiments with the aim to measure the spontaneous polarization in GaAs NWs, using NWs containing regions both of cubic zincblende as well as hexagonal wurtzite crystal phase.
• WP1: developing a low temperature in-situ electrical Transmission Electron Microscopy (TEM) holder
• WP2: sample fabrication for electrical in-situ TEM
• WP3: low temperature and transport experiments
WP1
Three prototypes have been made for the cryogenic liquid He electrical TEM sample holder. The first prototypes combined relatively high heat losses and a high weight of the He dewar. Therefore, a third prototype was developed where the conception of the He dewar was changed, improving both it’s thermal insulation and weight.
The third prototype is now ready and many cryogenic tests have been performed on this prototype, improving it step by step. 4K can now be reached during 17 min.
In WP2 we have advanced on the membrane fabrication, making membrane-chips compatible with different TEM holders and therefore TEM installations. We have acquired holders to perform a local back side etching, to render devices transparent by a backside etching process, while protecting the device side from the etching solution. We have published a review of our fabrication protocol and studies that were enabled by this technology, article 8.
At present, the most challenging aspect of this project appears to be the effect of the electron beam on our sample, especially for such delicate phenomena like Coulomb Blockade.
Therefore, we have started to work at samples containing many charges, to see if their properties can be reliably measured by in-situ TEM at room temperature. This will already constitute a major advancement in material characterization.
We focus on the following topics for WP3:
p-n junctions in NWs.
This is a model system for charge related phenomena, that is also interesting on its own accord, for example with respect to NW solar cells.
Al contact on Ge and SiGe NWs.
We have studied the exchange reaction between Al metal contacts on Ge and SiGe NWs, and observed that the Ge from the NW is replaced by Al. This is an interesting system for transport because the interfaces are very well defined and we can make a Ge QD of deterministic size using in-situ TEM (article 1).
InAs/InP NW heterostructure. We aim to use this system as a model system for proof of principle experiments of Coulomb blockade in the TEM.
GaN/AlN NW quantum dots.
We have studied the correlation of electro-optical properties with structure in GaN/AlN NW’s. Moreover, in-situ biasing combined with micro photoluminescence (μPL) allowed modifying the emission energy of a single GaN QD in a GaN NW (article 5). We have performed in-situ experiments on these samples to measure the internal fields and their change with applied bias using TEM techniques.
GaAs spontaneous polarization studies by holography.
To allow measuring a single charge, we will need to be able to measure very small electric fields. As a model system of very small internal electric fields, we have performed experiments with the aim to measure the spontaneous polarization in GaAs NWs, using NWs containing regions both of cubic zincblende as well as hexagonal wurtzite crystal phase.
We start to be able to do in-situ biasing without altering the object electrically. We have promising results of in-situ biasing combined with 4D STEM. We expect that this will allow us to map electrical properties in a contacted material quantitatively at room temperature. We expect to demonstrate these methods on several material systems. With the development of the cold holder, and contacted nanowire samples demonstrating Coulomb blockade, we will then assess the possibility of detecting a single charge with nm spatial resolution.