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Enabling Practical Wireless Tb/s Communications with Next Generation Channel Coding

Periodic Reporting for period 2 - EPIC (Enabling Practical Wireless Tb/s Communications with Next Generation Channel Coding)

Reporting period: 2019-03-01 to 2020-08-31

Wireless communication is a key technology of our information society and there is a continuous demand for higher throughput, higher spectral efficiency, lower latencies, lower power and large scalability on communication systems. This imposes large challenges on the baseband signal processing. Channel coding, or forward error correction (FEC), is a crucial technology component of any digital communication system. FEC provides reliable communication in the face of noise that corrupts the transmitted signal, but does at the expense of decreased information throughput and increased implementation complexity. FEC is a major source of power consumption, silicon area and largely contributes to the overall latency and throughput limitations in baseband signal processing. Beyond-5G use cases are expected to require wireless data rates in the Terabit/s range in a power envelope in the order of some Watts. In the past, progress in microelectronic silicon technology driven by Moore’s law was an enabler of large leaps in throughput, lower latency, lower power etc. However, we have reached a point where microelectronics can no more keep pace with the increased requirements from communication systems, especially in energy efficiency for wireless transceivers, which have tightly constrained power and energy budgets. The complexity of implementing advanced FEC schemes to operate at Tb/s data rates is a huge challenge. To achieve excellent communications performance, advanced channel coding schemes are mandatory. Turbo-, LDPC-, and Polar Codes are the most advanced channel coding schemes known today that exhibit excellent communications performance. However, this comes at the cost of large implementation challenges, especially when targeting throughput towards 1Tb/s under stringent power constraints. The EPIC project addresses these challenges and develops an implementation-ready FEC technology for Turbo-, LDPC-, and Polar codes that meets the cost and performance requirements of a variety of potential wireless Tb/s use-cases. EPIC methodology differentiates itself by combining code construction, decoding algorithm design and architecture/implementation in a holistic way so that optimization can be carried out jointly over a larger domain. The primary goals of the project are:
• to advance state-of-the-art and design next generation FEC for wireless Tb/s technology and Beyond-5G systems.
• to devise a disruptive FEC design framework to unify algorithmic and implementation domains.
• to validate and demonstrate the developed FEC technology in virtual silicon tape-out and provide first-in-class wireless Tb/s FEC architecture blocks.
• to put the scientific excellence and contributions to wireless industry in the domain of B5G standardization and technology development at the centre of the project execution.
EPIC key performance metrics (KPI) in advanced semiconductor technology nodes, i.e. 7nm, are throughput in the order of 1 Tb/s, an energy efficiency of about 1 pJ/bit, and an area efficiency > 0.1 Tb/s/mm2, while meeting communications and flexibility requirements derived from selected EPIC use-case.
The project started with a thorough search of leading industry standards, business platforms, and emerging applications that resulted in a wide range of Tb/s use cases. The use cases we considered were examples to derive cornerstones for communications performance, code rates, flexibility and implementation performance requirements from which we derived the EPIC KPIs. Since there is no silver bullet that matches all code classes, each code class was treated separately. For each code class, we identified and extensively investigated promising codes, code construction techniques and architectural templates in a cross-layer approach. Finally, we performed micro-architectural optimizations and virtual silicon implementation. In total we ran 19 virtual silicon implementations in three different technology nodes, i.e. 16nm FinFET, 22nm FD-SOI and 28nm FD-SOI. Although we were not able to implement the decoders in 7nm, we could demonstrate that for selected decoders some of the EPIC KPIs could be already fulfilled in 16nm. Extrapolations to 7nm show that EPIC throughput and area goals are very feasible for all code classes. The EPIC energy efficiency goal is also achievable for LDPC and Polar codes in 7nm. Only power density is still unsolved when the area density of advanced technology nodes is fully exploited. The power density challenge could be solved by exploiting voltage scaling in combination with multi-core approaches. EPIC also performed many dissemination activities. However, these activities were strongly hampered in the second period by the Covid-19 situation. Dissemination activities include involvement in standardization efforts, participation in many workshops, organizing of special sessions in various conferences and scientific publications.
We developed new solutions for all three code classes that go far beyond state of the art with different degree of novelty.
For turbo code we investigated: a new architecture-aware interleaver design that lowers the error floor and enables flexibility for unrolled high throughput architectures; a new low complexity soft-output decoding algorithm that largely reduces the implementation complexity at negligible degradation in error correction capability; a new high throughput unrolled architectural template and its virtual silicon implementation that outperforms state of the art by 2 orders of magnitude in throughput and one order of magnitude in area efficiency with outstanding communications performance.
For LDPC codes we investigated: new protograph based LDPC block codes that are optimized for low number of iterations and frame interleaved architectures and corresponding spatially coupled LDPC codes; architectural templates for unrolled block LDPC decoder, multi-core frame-based block LDPC decoder, unrolled layered block LDPC decoder, layered windowed SC-LDPC decoder, unrolled window SC-LDPC decoder and a LDPC decoder exploration framework that automatically generates these decoder architectures; virtual silicon implementations for all architectures and an in-depth investigation of the trade-offs and comparison of these different architectures, that go especially w.r.t. implementation efficiency far beyond state-of-the-art.
For polar codes we investigated: new codes that are generated via density evolution; SC, SCL, SCL-CRC and majority based decoding algorithms and advanced quantization techniques that largely reduces the implementation complexity; unrolled SC and SCL architectures with optimized register balancing, single core and multi-core architectural templates and a polar decoder exploration framework that automatically generates decoder architectures; virtual silicon implementations for all architectures and an in-depth investigation of the trade-offs and comparison of these different architectures, that go especially w.r.t. implementation efficiency far beyond state-of-the-art.
EPIC results provide a framework and database to efficiently assess the most important soft-information based FEC techniques as fundamental enabler of practicable beyond 5G wireless Tb/s solutions.