Periodic Reporting for period 1 - SERENA (gan-on-Silicon Efficient mm-wave euRopean systEm iNtegration plAtform)
Reporting period: 2018-01-01 to 2019-06-30
In WP2, the 39 GHz front-End MMIC have been specified and designed, the packaging have been discussed and constraints were integrated at the design phase. After the successful “preliminary design review (PDR)” and the corresponding “critical design review (CDR)”, and the reception of appropriate wafers from EPIGAN, the first manufacturing run (RUN1) of the 39GHz front-end MMIC started and triggered the production phase. The fabricated front-end MMIC have been characterized and the performance is in line with simulated results. The MMICs have been sent for embedding in the integration modules.
WP3 mainly focuses on the development of the core IC for the 39 Ghz beamforming chip as well as the bias control chip needed for the PA device. Having set the basic electrical specifications of the core IC in WP1 as well as the pin assignment/footprint, the electrical design started. Preliminary simulation results established the proper operation of the beamforming chip so the final electrical design of the component was deployed. Full and detailed electrical simulations including corner/ Monte Carlo analysis, temperature and supply variation followed and confirmed the compliance of the beamformer design to the specifications defined earlier. A similar approach was followed for the bias control IC. Both the beamforming and control IC were taped-out and fabricated. The fabricated beamformer IC have been electrically characterized and are fully functional and reaches the performance as set forth in the specifications.
In WP4, starting from the target specification for the GaN-on-Si based E-/W-band single-chip front-end MMIC the key circuit functions were simulated and some tentative layouts of those parts were designed. It would be possible to design a W-band multifunctional front-end fulfilling the target specifications. The EM-simulations of the passive parts took greater effort than originally anticipated and thus the tape-out was a bit delayed. The finalised circuit layouts incl. the individual sub-parts as breakout circuits were taped-out and the wafers were launched for fabrication. The wafers are still in fabrication and first results are expected soon. Based on the specifications of the system the specifications of the package were derived in WP5. The packaging technology was characterized electrically based on EM field simulations and the measurement of test structures fabricated in the PCB embedding technology. The processes for the embedding of RFICs with different pad metallization and air bridges were developed and tested. In WP6, an implementation proposal for the 5G proof-of-concept demonstrator has been finalized. The key element of the W-band demonstrator, a MMIC to waveguide transition, have been designed and disclosed. WP7 is responsible for the internal and external communication strategy as well as for exploitation. WP8 focuses on the operational management and the technical vitality of the SERENA project.
energy efficiency increased by a factor of 10; size reduction by a factor of 4; cost reduction by a factor of 10; significantly reduced design time/complexity; transmit output power by a factor of 4 to 10; power consumption reduction by a factor of 2 to 5; wireless area capacity (bit/s/km 2) increase by 10 to 100 times.
SERENA will contribute to doubling the economic value of semiconductor component production in Europe within the next 10 years by a two-pronged approach. First, SERENA spans the whole electronics manufacturing and supply chain (from wafers to system providers) and world class academic institutions. Second, the SERENA integration platform will enable “mass customization” of advanced mm-wave systems, where the front-end circuitry can be adapted for specific market needs. The claimed relative system level improvements are to be benchmarked towards state-of-the-art GaAs and SiGe solutions available as of April 2016. Currently SERENA has been advancing the available output power at 39 GHz both for the high-power GaN-on-Si MMIC as well as from the SiGe beamformer RFIC. The current published state-of-the-art at 39 GHz is 26 dBm saturated output power from a CMOS technology. For a complete array the current published state-of-the art. At the system level current state-of-the-art is about 40 dBm of linear EIRP from a 64-element antenna array using SiGe beamformers [Y. Yin, et. al. “A 37-42 GHz 8x8 Phased Array for 5G Communication System with 48-50 dBm EIRP”, Proceedings of the IEEE International Microwave Symposium, 2nd-7th June 2019, Boston, US]. Compared to these results the SERENA project are currently advancing the available output power for a 39 GHz beamforming system with a factor of 10. This result is based on the characterised output power from the fabricated GaN-on-Si MMIC front-ends. Since the inception of SERENA, 5G mm-wave systems have been commercially deployed in the US (at 28 GHz by Verizon) and many operators are running field trials (both at 28 GHz and 39 GHz). Furthermore, 3GPP have ratified the 5G NR standard for sub 6 GHz and above 24 GHz. Mm-wave 5G is happening now and the coming years will give a rapid evolvement of 5G mm-wave radio base station products for various use cases: fixed wireless access, enhanced mobile broadband etc. There is currently a strong market pull which will strongly contribute to the exploitation of the SERENA technology.