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Mont-Blanc 2020, European scalable, modular and power efficient HPC processor

Periodic Reporting for period 2 - Mont-Blanc 2020 (Mont-Blanc 2020, European scalable, modular and power efficient HPC processor)

Reporting period: 2019-06-01 to 2021-03-31

Mont-Blanc 2020 was the last of a long series of projects. The initial concept when we started in 2011 was very disruptive: leveraging mobile (Arm) chips and their power-efficiency to run HPC applications. The successive Mont-Blanc projects have witnessed and accompanied the rise of Arm processors in servers.

Whereas the previous Mont-Blanc projects pioneered the development of prototype HPC systems based on existing Arm processors and of the matching software ecosystem, Mont-Blanc 2020 focused on processor design. Our vision was to stimulate the European industrial capacity in processor design and boost the skills necessary for chip design, so as to contribute to the creation of a complete European value chain for high performance processing - and therefore to European sovereignty in the provision of HPC technology.

This is completely in line with a key objective of the EuroHPC JU: promoting HPC systems based on home-grown technologies, so as to develop Europe’s strategic self-reliance, boost European industry and the European job market. As part of this, the European Processor Initiative (EPI) ambitions to deliver an indigenous HPC processor, as well as an embedded processor for automotive and other AI applications by 2025. Mont-Blanc 2020 is upstream of EPI. The objective of Mont-Blanc 2020 was to start developing building blocks (IPs) for an HPC processor. The team designed and demonstrated ASIC modules, and this IP will be reused and productized within EPI. In that sense, EPI relies on the work done in the Mont-Blanc 2020 project.
The Mont-Blanc 2020 project has achieved several results on scientific and technological plans:
- Scalable Vector Extension, SVE-enabled core performance modelling: the MB2020 choice for the compute unit was to use ARMv8 ISA. Especially, the new SVE optimized for Arm based servers and HPC/AI applications. The main work performed was a) the new Gem5 simulation framework was delivered and published, b) a complete scalable processor model matching the MB2020 vision
- MB2020 Veloce demonstrator: The purpose of the demonstrator flow is to verify the projects components in a real-world application environment and extract meaningful performance metrics
- A low power Network on Chip (NoC): The Network on Chip is an essential module of the next high-performance processors and must handle a very high message rate and bandwidth while maintaining low latency. In the Mont-Blanc 2020 project, we focus on designing a NoC generator based on the new CHI protocol that can handle up to 128 ARM cores and different memory types.
- Processor Blueprint for HPC: The MB2020 blueprint focuses on the main functions of the processor: cores, memory hierarchy and external interfaces. It provides the sizing and the topology connecting the main IPs developed in the scope of MB2020 project. The blueprint also proposes an optimized usage of the MB2020 IPs respecting the requirements of the common processor platform
- Acceleration interface and programming model for deep learning inference and computer vision: The supplementary mission of MB2020 was the use cases for automotive and edge computing to explore other markets than HPC to reinforce the economical sustainability of a homemade processor. To this end, the MPPA FPGA Emulation Platform has been made to demonstrate the integration of the MPPA acceleration tile into an ARMv8-based SoC and interconnect standards, first on the architecture level, then on the software stack for offloading.
Our most significant exploitations are the following:
1. The IP for NoC developed in Mont-Blanc 2020 is part of the next generation EPI processor.
2. MUSA was released as part of EPI deliverable D5.1 MUSA Multi-Level Simulator for ARM ISA.
3. Support for the Arm Scalable Vector Extension (SVE) ISA in the gem5 performance simulator is included in the gem5 20.0 official open source release.
4. The NoC and related NoC IPs have been integrated in the Atos IP portfolio, ready for re-use in future commercial or research projects.
5. Contribution to Kalray tools/products based on MPPA.
The Mont-Blanc 2020 team dedicated a lot of energy to promoting the project and its outcomes. One of the main dissemination highlights for MB2020 is the coordinating role played by the project to organise joint activities with other European Exascale projects, and particularly joint booths at tradeshows – until Covid-19 struck. A total of 48 dissemination activities were held during the lifetime of the project, including 22 peer-reviewed publications, 6 invited talks, as well as booths at tradeshows, presentations at workshops, peer-reviewed posters, hackathons, tutorials, and a MOOC.
One of the strong points of the successive Mont-Blanc projects has been industry/academia collaboration, and Mont-Blanc 2020 was no exception, with a team of 3 core partners with complementary profiles (Arm, Atos, BSC), 3 SMEs (Kalray, Semidynamics, Sipearl) and prominent research partners (BSC, CEA, JSC). This was instrumental in ensuring that the homegrown technologies developed within the project are or will be actually rolled out in European and international systems and further projects:
• all Mont-Blanc 2020 partners have declared Exploitable Results,
• all “commercial” Mont-Blanc 2020 partners have already integrated or will integrate some outcomes of the project in their products/offer,
• all academic Mont-Blanc 2020 partners are already using or planning to use some outcomes of the project for further research projects.

The top MB2020 impact is without doubt that the project provided the foundation to develop a family of European-grown processors, and in particular for a processor that can power the future European Exascale supercomputers. MB2020 developed IP for a low power Network on Chip (NoC). This IP will be included in the next generation EPI processor. Our NoC and related NoC IPs are also integrated in Atos’s IP portfolio that will serve future commercial and research projects.

Beyond the IP portfolio for a European SoC, it was equally important to reinforce the skills necessary for chip design. The consortium therefore made important efforts to share and perpetuate the knowledge, methodology and tools used/developed by the project for processor simulation and virtual prototyping, i.e. the tools that allowed our researchers to test applications and evaluate future performance prior to silicon availability. We developed a unique co-design methodology for SoC infrastructure verification and optimization, building a bridge between the CAD tools used by our industrial partners and the open source tools used by our academic partners.
The Consortium members shared this knowledge through many workshops, tutorials and hackathons. And many of the features we developed for our Simulation Framework are already used outside of the project. For example, MB2020 was instrumental in the implementation of SVE instructions in gem5, which is part of the official open source release 20.0 of gem5. Another example is the SVE-related improvements to the MUlti-scale Simulation Approach (MUSA) developed within MB2020, which are used within EPI.
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