Negative capacitance field effect transistors functioning as low power steep slope switches has been (and still is) a controversial topic of research since 2008 when it was first conceptualized theoretically. Since then, several attempts have been made to demonstrate the effect experimentally using organic and inorganic ferroelectric gates. The interest in the field has considerably increased since the discovery in 2011 that HfO2, a Si-compatible gate dielectric used to scale advanced CMOS, is ferroelectric. Since then a large number of reports was published showing hints of steep slope transistors (for a review, see Kombayashi, Appl. Phys. Express 11, 110101 (2018)). However, it has been difficult to make the correlation of the observed steep slope transfer characteristics to the negative capacitance (NC) effect. Perhaps the best evidence that the negative capacitance exists in HfO2-based ferroelectrics has been recently published in Nature (M. Hoffman et al., Nature 565, 464 (2019)). The striking observation is the S-shaped polarization-field curve revealed by transient measurements. While this is an important development, the practical use of this effect in transistors is still unknown. Most of the transistors with ferroelectric gates inherently suffer from unwanted hysteresis, which is prohibitive for high volume manufacturing. Moreover, ferroelectricity and consequently NC effect in HfO2 becomes obsolete as the gate scales down to a ~ 3 nm thickness, which poses additional difficulties in using HfO2 ferroelectrics for NC steep slope switches.
An alternative solution has been proposed by us, based on the concept of negative quantum capacitance (NQC) of graphene (G. Shi et al., Nano Lett. 14, 1739 (2014); P. Tsipas et al., Adv. Electron. Mater. 2, 1500297 (2016)) and other 2D materials (H. Choi, Appl. Phys. Lett. 109, 203505 (2016)) as a result of electron correlation effects. The NQCFET featuring a graphene layer integrated in the gate of conventional Si MOSFETS, produces non-hysteretic characteristics and has good prospects for scaling. First results obtained in ERC AdG SMARTGATE have shown that NQCFET shows steeper slopes compared to control FETs. Our work in the POC GR-GATE project confirms our previous observations and provides evidence of subthermionic subthreshold slopes (<60 mV/dec) for graphene-gated transistors for a drive current range of more than 3 orders of magnitude. Based on these results an international patent application has been filed for the NQCFET. Technology valorization performed in collaboration with major European graphene technology organization shows that the main obstacle in high volume manufacturing of NQCFET is the Cu contamination due to wet transfer of graphene in the gate of transistors during FEOL processing, a contamination that cannot be sufficiently mitigated by Cu diffusion barriers such as Si3N4. Cu contamination is not compatible with Si CMOS processing so it is necessary to circumvent this problem. Using a dedicated processing line and tools could be an option which however increases cost. Using dry transfer methodologies could be another option which however raises concerns about the quality of the transferred graphene. Large area transfer based on roll-to-roll approach, wet and dry, has been manifested. However, this approach is compatible with transfer on flexible rather than rigid substrates, i.e. wafers [Appl. Phys. Rev. 5, 031105 (2018)].
Clearly, the possibility of high volume manufacturing of our NQCFET critically depends on the progress in the automization and Cu-free transfer process of graphene. In parallel, the NQCFET needs to demonstrate clear advantages with competing NC devices based on ferroelectric HfO2, preferably with the contribution of the wider research community including the research and development departments of key integrated device manufacturers. Once this is done, the next step for industrialization are as follows: i)Seek funding for NQCFET fabrication runs in an environment which is better suited for high quality wafer scale processing of such devices with respect to contamination, yield and other indicators for manufacturability; ii) Actively participate in the search for reliable and high quality wafer scale transfer of graphene as the main remaining obstacle towards industrialization of graphene in conventional electronic device applications; iii) Actively participate in the search for Cu-free and CMOS compatible substrates for graphene growth and/or direct growth of graphene on silicon/silica substrates; iv) Identify potential applications for those devices in the back-end of line and establish them there, e.g. by utilizing an European pilot line project as a first demonstrator; v) After demonstration of NQCFETs in a back-end of line application and the development of scalable transfer technology identify front-end of line applications for which the concept offers enough potential in terms of device performance that can justify additional fabrication costs coming with this concept.
