Deliverables
This will provide architecture of the storage and memory access backend used for Maestro. This deliverable will also cover the design of data object mapping as per the storage integration design.
An API and usage document based on the requirements of the applications provided by WP2. This document will serve as a review vehicle for further feedback from applications and workflows.
This report will document the strategy for innovation management and exploitation and comprise a detailed plan for its implementation.
A report containing an updated description of the existing HPC workloads within the project, and describing the requirements they impose on the middleware and API designs, and proposing a resultant API design.
A report describing the design of extensions of SelFIe and Mero
Definition of the quality control processes and templates for internal verification and document review for all project results and deliverables. This will be a living document that is updated throughout the project when necessary.
An initial overview of the existing HPC workloads for applications within the project, and the requirements they impose on the middleware and API designs.
A report describing the selected applications and how they will be used in the demonstration of the Maestro development
A specification, API and usage document describing proposed transport mechanisms
This report will document the strategy for dissemination and provide a detailed plan for its implementation.
A report describing the tests objectives
A reference implementation of the core middleware with the central CDM infrastructure, MSM, LDO and PDO implementations, with all features functional, though without performance optimisations or consideration to advanced usage.
An initial version of the model workflows that will be used in middleware evaluation.
Full release of the transport mechanisms.
Provisioning of a web presence of the Maestro project as major channel for dissemination.
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Publications
Author(s): François Tessier, Maxime Martinasso, Matteo Chesi, Mark Klein, Miguel Gila
Published in: 2019
Author(s): Manuel Arenaz, Xavier Martorell
Published in: High Performance Computing - ISC High Performance 2019 International Workshops, Frankfurt, Germany, June 16-20, 2019, Revised Selected Papers, Issue 11887, 2019, Page(s) 352-360
DOI: 10.1007/978-3-030-34356-9_27
