The primary objective of DIPSAP-II project is to demonstrate the feasibility of producing a European 32-bit floating-point DSP to satisfy the immediate needs of the space and certain industrial (eg automotive) markets. The development will be performed in such a way as to bring the ESPRIT/OMI results and practices into these market sectors. DIPSAP-II is a continuation of the OMI application feasibility study DIPSAP-I (6347), which proved paper feasibility of the approach (transfer and adaptation of an existing DSP design), identified (common) requirements and design synergies between space and automotive fields and established basic DIPSAP design concepts within the OMI framework.
DIPSAP-II aims to demonstrate hardware feasibility. Initially, demonstrators (boards) using predominantly commercial components will be developed proving OMI architectural and communication concepts. In parallel the two DIPSAP enabling technologies for processing (DSP core) and communication (SMCS, see below) will be developed and first prototypes produced. Extensions to the DSP design tool SPRITE/Cathedral (2260) to support these technologies will be investigated. In a second stage the components in the demonstrators will be replaced by logically equivalent OMI-conformant chips. Following tests, the chips and demonstrators will be redesigned and final OMI application pilot demonstrations produced.
The space demonstrator will address a multi-processor "network" architecture (for eg stereovision applications) of direct interest also to non-space applications. Here the emphasis will be placed on the demonstration of OMI interfaces and the technology "independence" of macrocells through transfer and realisation in different process technologies. The automotive demonstrator will address miniaturization aspects (on chip integration, MCM) necessary for high performance applications such as vehicle guidance. Here a demonstration of on-chip integration of macrocells from different sources is intended.
The key element of the network architecture is a processor-independent logical entity called the Processing Element (PE). The goal is to define a processor architecture where any OMI processor could be used as CPU. Minimum design and development effort is required to change to a different CPU. In terms of hardware realisation, the PE is a logical entity which may be implemented as several distinct chips (eg using space qualified memories), as a Multi-Chip Module (MCM), or as a single chip depending on the complexity of its CPU core and the maturity of the target process technology. Under the DIPSAP-II project PEs based on DSP will be realised, with PEs based on eg SPARC (SMILE 6142) foreseen.
The Scalable Multi-Channel Communications Subsystem of SMCS (part of each PE) provides a standardised data or control link interface between the CPU of the PE and the routing system of the reference network architecture. It is a scalable concept based on 16 (for micro-controller or 1750-type processor), 32 (for RISC processor and DSP data transfer) and 48 bit (for DSP program transfers) system interfaces. Under DIPSAP-II, the SMCS will be developed using existing and developing standards. It is intended to base the network interfaces on the DS-links implementation of the P1355 Standard being developed by INMOS within the HIC project (7252). In DIPSAP-II, the SMCS will be designed in an OMI conformant format and produced in silicon.
92045 Paris La Defense
92045 Paris La Défense