Periodic Reporting for period 1 - SIPhoDiAS (Space-grade Opto-electronic Interfaces for Photonic Digital and Analogue Very-high-throughput Satellite payloads)
Reporting period: 2020-01-01 to 2020-12-31
SIPhoDiAS aims to advance these components to address opto-electronic performance, size and power, and at the same time, demonstrate their reliability targeting a TRL 7, enabling the next generation of VHTS P/L systems. SIPHODIAS invests in state-of-the-art SiGe BiCMOS, GaAs and InP manufacturing technologies as well as innovative assembly and module packaging to deliver high-speed digital optical transceivers, high-bandwidth electro-optic modulator arrays and miniaturized analogue photodetectors. The optical transceivers are designed to deliver >100 Gb/s optical interconnects within the P/L digital processor whereas modulators and photodetectors will enable operating frequencies in the Q and V-band respectively. By realizing its S&T objectives, SIPhoDiAS will present for the first time photonic P/L systems that hit the right performance and SWaP targets and enable the sustained entry of photonics into modern communication satellites.
• Complete definition of system architecture and module requirements considering the satellite photonic payload application.
• Completion of the critical design of the 112 Gb/s optical transceiver (OTRx) chipset consisting of a 4x 28 Gb/s VCSEL driver and TIA receiver circuits. Successful tape-out was launched in IHP SG13RH process and IC delivery is planned within 2021.
• Completion of the critical design of the 112 Gb/s (4x 28 Gb/s) optical transceiver (OTRx) module including optical, RF and mechanical design. Parts procurement and module assembly, integration and test launched. Module delivery is planned within 2021.
• Completion of the critical design of the high-bandwidth GaAs modulator array including mechanical, optical and RF design. The module hosts two modulators with each modulator expected to deliver a bandwidth in excess of 50 GHz. Module delivery is planned within 2021.
• Completion of the critical design of the high-bandwidth analogue photodetector including mechanical, optical and RF design. The module is expected to deliver a bandwidth of 40 GHz. Module delivery of the first Ka-band module is planned within 2021.
• The 112 Gb/s OTRx IC chipset is expected to meet a power consumption target of 161 mW which corresponds to an efficiency of 5.7 mW / Gb/s per channel.
• The 112 Gb/s OTRx module is expected to weigh <6.5 grams and consume a PCB area of ~675 mm2. Packaging is compliant to the COBO standard for mid-board optics transceiver modules.
• The GaAs twin modulator array is expected to deliver a bandwidth of 50 GHz per modulator within a small form factor package with a footprint of 9 cm2 and an aggregate bandwidth per unit area of >7 GHz / cm2.
• The analogue photodetector is expected to deliver a bandwidth of 40 GHz within a package that weighs <16 grams and occupies an area of 2.35 cm2 corresponding to a bandwidth per unit area of ~17 GHz / cm2.
The achievement of these targets are fully in line with the project system objectives and the end-user roadmap as well as they constitute significant advancements in the application area of hi-rel digital and analog O/E modules. Within the second year of the project execution these targets will be verified through the prototype assembly, integration and testing.