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Memory technologies with multi-scale time constants for neuromorphic architectures

Periodic Reporting for period 1 - MeM-Scales (Memory technologies with multi-scale time constants for neuromorphic architectures)

Reporting period: 2020-01-01 to 2021-12-31

Neural processing in the nervous system occurs naturally over multiple time scales ranging from milliseconds (axonal transmission) to seconds (spoken phrases) and much longer intervals (motor learning).

The main objective of the EU H2020 MeM-Scales project is the joint co-development of a novel class of algorithms, devices, and circuits that reproduce multi-timescale processing of biological neural systems, for building a novel class of neuromorphic computing systems that can process efficiently real-world sensory signals and natural time-series data in real-time (e.g. for low-power and always-on IoT and edge-computing applications that do not need to connect to the cloud), and to demonstrate this with a practical laboratory prototype.

Our scientific and technological objectives can be summarized as follows:
1. To study the theory, and develop algorithmic and architectural innovations for realizing adaptive and robust multi-timescale neural processing on mixed-signal analog/digital neuromorphic processors comprising both volatile and non-volatile memory devices to implement the synaptic circuits and TFT-based neurons.
2. To develop novel hardware technologies that support on-chip learning with multiple time constants, both for synapses (volatile memory option combined with non-volatile memory, Electrochemical metallization, vacancy-type oxide-based memories, and Phase Change Memory), and neurons (TFT option exploration, plus integration with other devices).
3. To study and develop an ultra-low-power, scalable and highly configurable neuromorphic computing processor capable of online, life-long learning for personalized neural learning and adaptation algorithms.
4. To validate and demonstrate the project developments on realistic fully personalized edge application cases (by both simulation and board prototyping).
During the first twenty-four months of the MeMScales project the focus was on setting up the manufacturing processes for the multi-time scales neuron and synapse circuits based on resistive memory devices. We also started the development of concepts, formal models, and algorithms that enable analog neuromorphic microchips to be used in tasks which need to integrate input information over several timescales. For instance, in speech processing it is necessary to integrate information across timescales from a few milliseconds (phonemes) to hundreds of milliseconds (words) to seconds (sentences) and beyond (argumentation context). Similar challenges arise in most real-life signal processing tasks (for instance medical, engineering, environmental monitoring). A survey of available approaches in theory-building concerning timescales in the fields of computational neuroscience, mathematics, machine learning and computer science has been produced, it constitutes a guiding for the technological and circuit developments. First memory devices with tunable volatility (retention times from µs to minutes), have been demonstrated. An early tape-out of test circuits in 130nm foundry CMOS with hafnium oxide-based resistive memories integrated between M4 and M5 was realized that contains already two neuromorphic CMOS test chips useful for the final demonstrator and many test-structures to validate the possibility of on-chip learning. The first processed wafers are available since December 2021. A second tapeout dedicated to the Thin Film Transistor (TFT) technology was realized, the leakage current approximation of such a thin film stack is one of the most accurate available. A multi-timescale neuron has been designed and fabricated, it is the first flexible neuron that exploits thin film’s low leakage currents which will result in a neuron capable of firing with different timescales. This will result in a neuron capable of slow timescales which are very difficult if not impossible to attain for CMOS circuits. Based on our results 10 scientific papers (4 conference papers and 6 journal articles) and 4 patents have been already accepted for publication.
The technologies designed in MeM-Scales target the IoT / edge computing markets, which is expected to grow sharply in the coming years. The market for edge computing chipsets is projected to surpass 50 billion USD by 2025; in particular, the market is projected to outstrip cloud computing chipsets (e.g. devices based in data centers) by a factor of three.
MeM-Scales is focused on event-based or spiking neural network (SNN) or spiking neuromorphic applications where a diverse range of time scales is present and required. So, we mostly aim at streaming applications where the input/sensor data is sampled in a near-continuous stream and information of the past has to be stored across multiple time horizons. One major application domain where this is valid is in autonomous navigation and moving vehicles such as robots, drones and even cars. In this-case, one can take advantage of heterogeneous collection of video cameras, radar sensors and potentially also lidars. Another major application target domain are sensor-based healthcare and life-style systems such as smart patches, smart wristbands, smart glasses and even smart shoes. Also in that case, we can make use of sensory fusion by combining a heterogeneous set of sensors for collecting information such as ECG, EMG, bio-impedance streams and potentially also brain signals through EEG sensors and neuro-probes.
Major progress beyond the state of the art is expected by merging all the innovations at the levels of algorithms, non-volatile / volatile devices, neuromorphic circuit designs, and scalable CMOS and TFT connection schemes in a cross-disciplinary effort towards the realization of multi-time scale spiking neural processing systems. MeM-Scales targets at deliver ultra-low power autonomous life-long on-line learning systems which will have a tremendous impact on the above mentioned edge computing applications domains.
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