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The MareNostrum Experimental Exascale Platform

Deliverables

Full emulation prototype release

In this deliverable the full prototype will be made ready running some instances with many scalar processors other instances with scalarvector Second and final release of the FPGA shell The applications from WP5 will be executed in the emulation environment An evaluation of the selfhosted accelerator will be performed with a comparison to CPUonly and when possible GPU execution environments The evaluation criteria will include performance ease of programming and tuning

Linux with initial host interface release, based on the requirements document

In this deliverable an initial release of the Linux OS targeting to run on the scalar core in the selfhosted accelerator will be released The selfhosted OS will be completely designed and specified with respect to all packages and any porting of support packages will have begun Container support is one of the major additional packages that will be in development for this milestone Also compiler support and initial generated code will be available for traditional HPC workloads

Emulated accelerator second release with full capacity of inter-accelerator communication

This is the second release of the FPGA implementation of the accelerator with capability to run many scalarvector accelerators that can fully communicate with the other accelerator modules

FPGA RTL revision 1 release. Complete verification environment

In this deliverable an initial release of the accelerator RTL will be made available which will serve as a midterm checkpoint for the RTL design process This will include the initial integrated scalar vector cores with some basic intraaccelerator communication Additionally the full verification strategy and plan will be made available pinpointing the various methodologies used while matching the design specifications

Application ported

In this deliverable all applications have been identified that will be ported to the emulation platform The traditional and emerging HPC applications will be running on the emulation platform The final phase will focus on application performance evaluation and debugging

First AIT release

In this deliverable the first release of the Automatic Integration Tool will be delivered in which the system will be able to provide a basic framework for designing a microarchitecture and based on that information following the traditional FPGA flow until completing the process by the automatic bitstream generation

Exploitation strategy

Outlining the exploitation strategy and how this will be implemented

Project Management and Quality Guidelines

This deliverable will describe the projects internal management procedures detailing the projects Quality assurance process as well as a detailed Risk evaluation and internal communication tools and mechanisms

Benchmark suite of HPC applications

In this deliverable the initial benchmark suite used to drive the hardwaresoftware codesign of the Exascale supercomputer will be identified

Dissemination and communication report

Presenting disseminationcommunication activities and their impact until M18

Dissemination and communication plan

Outlining the dissemination and communication strategy and how this will be implemented

Coyote as a RISC-V architectural Simulator - Final release

A complete functional and operative release of Coyote simulator will be delivered This version will include all the required features to model and simulate at least the targeted accelerator in the MEEP project ACME such as support for manycore architectures model and define different policies and strategies for the memory hierarchy NoC communication Moreover for facilitating the analysis of the simulation results Coyote will include the capability for visualizing and tracing results

Final dissemination and communication report

Summarising disseminationcommunication activities and their impact until M42

Emulation platform specification

The platform definition document motivates the selected FPGA hardware platform to be used for emulation together with the HW specs for the FPGA implementation of the RTL the FPGA shell and other required IP including the necessary IPs with a specific plan to the acquisition of each

Data Management Plan (DMP)

The DMP will describe the life cycle for all data sets that will be collected processed or generated by the research project It is a document outlining how research data will be handled during a research project and even after the project is completed describing what data will be collected processed or generated and following what methodology and standards whether and how this data will be shared andor made open and how it will be curated and preserved The DMP is not a fixed document it evolves and gains more precision and substance during the lifespan of the project It should include the following information iDescription of Data iiData CollectionGeneration iiiData management documentation Metadata ivIntellectual Property Rights and vAccessibility Data sharing archiving and preservation

Publications

The MareNostrum Experimental Exascale Platform (MEEP)

Author(s): Alexander Fell, Daniel J. Mazure, Teresa C. Garcia, Borja Perez, Xavier Teruel, Pete Wilson, John D. Davis.
Published in: Supercomputing Frontiers and Innovations, Issue 8/1, 2021, ISSN 2313-8734
Publisher: Publishing center of the South Ural State University
DOI: 10.14529/jsfi210105

Highly parallel GPU accelerator for HEVC transform and quantization

Author(s): Mate Cobrnic, Alen Duspara, Leon Dragic, Igor Piljic, Mario Kovac
Published in: 2020 International Conference on Image, Video Processing and Artificial Intelligence, 2020, Page(s) 81, ISBN 9781510639980
Publisher: SPIE
DOI: 10.1117/12.2581228

Coyote: An Open Source Simulation Tool to Enable RISC- V in HPC

Author(s): Borja Perez, Alexander Fell, John D. Davis
Published in: 2021 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2021
Publisher: IEEE

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