Secure and Assured hardware: Facilitating ESTonia’s digital society

Project Information

SAFEST

Grant agreement ID: 952252

DOI

10.3030/952252

Project closed

EC signature date 10 June 2020

Start date 1 January 2021

End date 31 December 2023

Funded under

• Twinning of research institutions

Total cost

€ 895 418,75

EU contribution

€ 895 418,75

Coordinated by

TALLINNA TEHNIKAÜLIKOOL
Estonia

Periodic Reporting for period 2 - SAFEST (Secure and Assured hardware: Facilitating ESTonia’s digital society)

Reporting period: 2022-04-01 to 2023-12-31

Summary of the context and overall objectives of the project

The overall aim of the SAFEST project is to enhance the scientific and technological capacity of Tallinn University of Technology (TalTech) in the field of Hardware Security, to be achieved through networking activities with its internationally-leading partners: University of Montpellier (UM/CNRS), Technische Universität München (TUM), Katholieke Universiteit Leuven (KUL), and Technische Universität Graz (TUG).

Hardware Security has been identified as a knowledge gap by several Estonian stakeholders (TalTech itself, Estonian Ministries, local companies, etc.) and contributes to several national strategies, most notably the national Cybersecurity Strategy. Understanding threats and creating assurances that the hardware utilized by the Estonian e-society is trustworthy are key objectives of the project.
Four main objectives have been set for this project:
Objective 1: Strengthen the research capability of TalTech and its partners in the area of Hardware Security
Objective 2: Promote TalTech's competitiveness through sustainable participation in collaborative research efforts
Objective 3: Raise the research profile of TalTech and the partners
Objective 4: Contribute to the safety aspects of e-Estonia

Work performed from the beginning of the project to the end of the period covered by the report and main results achieved so far

Networking activities of many different forms have taken place primarily in a virtual setting. The SAFEST project has organized two events in year 1, namely a summer school and a workshop, two summer schools in year 2, and a summer school and a workshop in year 3. The events were fairly well attended and covered all topical areas of interest for the project. Many other exchanges took place via numerous online meeting (i.e. Zoom conf. calls). The SAFEST project had 131 of such meetings, indicating a high level of cohesion and commitment of the project partners.
In terms of practical results achieved, these appears as jointly-authored publications of the SAFEST partners. For the purpose of this short report, we will highlight two articles:
- In “Hardware Obfuscation of Digital FIR Filters”, researchers from TalTech and TUM investigated how to protect digital circuits against reverse engineering practices. This work was published as a conference paper in the 25th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS 2022). This work has received a best paper award. An image related to this work is provided, where the reverse engineering view of the many connections of a circuit is given. This type of analysis is performed by both attackers and defenders, albeit with different goals, naturally.
- In “Design Space Exploration of SABER in 65nm ASIC”, researchers from TalTech and TUG investigated how to accelerate cryptographic operations in hardware. This work was published as a conference paper in the Workshop on Attacks and Solutions in Hardware Security (ASHES ’21). Here we highlight that this work is incredibly representative of the spirit of the Twinning collaboration in SAFEST: TalTech provided its expertise in chip design while TUG provided its expertise in security. Together, both partners worked on a chip that serves as a demonstrator of their effort. Furthermore, the cryptographic algorithm utilized in this work (SABER) is currently being considered for standardization, thus showing how relevant and timely the research on this topic is. An image related to this work is provided, where our tiny chip that measures only 1mm x 1mm has been photographed under a microscope.

Progress beyond the state of the art and expected potential impact (including the socio-economic impact and the wider societal implications of the project so far)

As a general trend, we expect more jointly authored publications between the partners with the goal to cover all topical areas identified in the initial project proposal. From the research articles that are currently under preparation, we assuredly expect progress beyond the state of the art in the following topics: hardware obfuscation topics (i.e. the ability to protect a circuit against reverse engineering); novel architectures for the generation of true random numbers (which are fundamental components of many cryptographic operations and signature schemes); and more silicon demonstrations of chips designed in cooperation between the partners.

The most important social impact of the SAFEST project is that a research group specialized in hardware security topics has been started and consolidated at Tallinn University of Technology. This group, led by Prof. Pagliarini, takes the role of consultant for any Estonian stakeholders that have to interface with that domain. Many local companies have already benefited from such consulting opportunities (TESTONICA LAB OÜ, Skudo OÜ, Golbriak Space), as well as the Majandus- ja Kommunikatsiooniministeerium which is the Ministry that coordinates cyber activities in Estonia.
As explicitly stated in the project proposal, our goal is to “put TalTech on the map” of who is who in Hardware Security.

Visual representation of a circuit under reverse engineering

Microscope image of the chip designed by TalTech researchers in cooperation with TU Graz