Work package 1: Design of readout circuits for MEMS that do not require neither biasing circuitry nor high bias voltage, incorporating the sensor into the ADC itself. The first proposals in this workpackage can be divided into two types:
a) The MEMS capacitor is used as a load in a ring-oscillator. This idea has been analysed at system level with behavioral simulations. The results were published in the international conference Austrochip 2022. It has been proved that the sensitivity of the MEMS is sufficiently high to achieve moderate resolution requirements, suitable for human-machine interfaces. Nevertheless, a limitation of this solution is the impossibility to implement differential architectures and the sensitivity to process and temperature.
b) The MEMS is included in a loop that regulates the oscillation frequency of a ring-oscillator with switched capacitor circuits. System level simulations have been performed showing proper results and a first test-chip has been fabricated. Experimental measurements will be done during the next months. It is expected to achieve an experimental resolution higher than the one simulated in the first idea with higher robustness against PVT variations. A journal publication is expected.
Work package 2: Implementation of scalable, compact and power efficient filter banks and power estimators. The basic building blocks of the filters are implemented usign time-integrators and signal handling based on asynchronous digital logic. The targeted objectives are an average power consumption lower than 100 nW per channel, and an occupied area lower than 5000 um2 per channel. A first approach at system level has been already simulated and published in Austrochip 2022. Also a first proposal of a low-pass filter has been taped out in a CMOS chip. It is expected to measure a sufficiently good filtering performance for feature extraction tasks with ultra low power consumption. A journal publication is expected with these measurements. Next, we want to implement a set of band-pass filters with power estimators compatible with spiking neural networks.
Work package 3: Using time-encoded based neuron cells for the proposal and implementation of neural networks that could be included into low-power classification stages of smart signal processing architectures, such as VADs. At this point of the research, two lines of research are being studied:
a) Proposal of neural network composed of a first layer with ring-oscillator based Multiply-Accumulate (MAC) cells followed by digital GRU units. It has been simulated for VAD tasks, with accuracy detection parameters (AUC) higher than 80% even within noisy environments. Power estimations from schematic simulations are only 24 nW for each neuron cell. These results have been submitted for publication to the 2023 ISCAS conference. A ring-oscillator based MAC cell has been taped out in a CMOS chip, under fabrication. The chip measurements will be submitted to a journal (e.g. IEEE Transactions on Circuits and Systems - II). We expect to build next a complete neural network on silicon, including ring-oscillator MACs, for complete characterization.
b) Neuromorphic approach for VAD, mimicking the performance of spiking neural networks with time-encoded based circuits. First simulations on this idea are being performed with behavioral models.
The main impact expected from this action is the contribution to making and keeping the EU at the forefront of microelectronics, artificial intelligence, and sensors with a growing financial market share.
