dEsign enVironmEnt foR Extreme-Scale big data analytics on heterogeneous platforms

Informations projet

EVEREST

N° de convention de subvention: 957269

DOI

10.3030/957269

Projet clôturé

Date de signature de la CE 31 Juillet 2020

Date de début 1 Octobre 2020

Date de fin 31 Mars 2024

Financé au titre de

• INDUSTRIAL LEADERSHIP - Leadership in enabling and industrial technologies - Information and Communication Technologies (ICT)

Coût total

€ 5 037 372,50

Contribution de l’UE

€ 5 037 372,50

Coordonné par

IBM RESEARCH GMBH
Switzerland

CORDIS fournit des liens vers les livrables publics et les publications des projets HORIZON.

Les liens vers les livrables et les publications des projets du 7e PC, ainsi que les liens vers certains types de résultats spécifiques tels que les jeux de données et les logiciels, sont récupérés dynamiquement sur OpenAIRE .

Livrables

Documents, reports (17)

Intermediate report of the compilation framework

Refined version of the report in D41 including actual interfaces of the alpha versions released for the software and the hardware compilation tool flows D43 and D44

Refined definition of the application use cases

This document describes the final version of the EVEREST application requirements based on revisiting the application use cases, starting halfway through the project schedule (M18).

Data management techniques: initial version

This deliverable summarizes the status of T31 T32 and T33 at month 18 It contains the initial definition of policies related to data layout communication and security and it reports the details of the intermediate status of the component The EVEREST API used by the virtualized runtime environment is defined in this deliverable

Intermediate runtime environment report

This report describes the features of the runtime environment released at month 18 where the integration interfaces with the autotuning framework and virtualization have been defined

Use case evaluation report

A detailed evaluation of the EVEREST applications optimized with the integrated design environment.

Refined specification of data requirements

This document describes the final version of the EVEREST data requirements based on revisiting the application use cases, starting halfway through the project schedule (M18), with insights from the initial activities in WP4.

Definition of the application use cases

This document collects the EVEREST application requirements This document will trigger the activities in WP6 as well as it composes the base of the final D24

Definition of the compilation framework

Early document with the definition of the DSL constructs for dataabstractions Task 41 the foreseen tool flow specification Task 42 details of the intended HLS flow and its extensions Task 43 a concrete proposal for the target language Task 44 This definition will allow for early feedback from applications partners

Final report of the compilation framework

Refined version of report D4.2 including interfaces of the beta integrated compilation tool flow (D4.6).

Definition of language requirements

This document collects the EVEREST language requirements This document will trigger the activities in WP4 and WP5 as well as it forms the base of the final D25

Initial dissemination plan

This deliverable describes the dissemination activities of the project In particular it describes the initial plan for the dissemination activities of the project and will be updated in D73

Intermediate dissemination report and updated plan

This deliverable describes the dissemination activities of the project and includes the report on the dissemination activities performed by the project partners during RP1

Refined specification of language requirements

This document describes the final version of the EVEREST language requirements based on revisiting the application use cases, starting halfway through the project schedule (M18) and with insights from the initial language development phase.

Final dissemination report

This deliverable describes the dissemination activities of the project and includes the report on the dissemination activities performed by the project partners during RP2 and the entire project.

Final runtime environment report

Documentation of the entire runtime environment, including auto-tuning, virtualization and decision-making engine with the variant selection.

Data management techniques: final version

This deliverable summarizes the work done in T3.1, T3.2, and T3.3 at the end of the tasks. It contains the updated and consolidated definition of policies related to data layout, communication, and security. Furthermore, it reports the architectural details and the characteristics of all the components implemented in the different tasks.

Definition of data requirements

This document collects the EVEREST data requirements This document will trigger the activities in WP3 as well as it composes the base of the final D26

Websites, patent fillings, videos etc. (1)

Project website

This deliverable will be the design and implementation of a website as pivotal communication and dissemination vehicle for the project technology and product announcements The web portal will be updated regularly with the latest information about the project its activities and intermediary results Google Analytics will be used to monitor the traffic on the public area of the website

Open Research Data Pilot (3)

Interim data management plan

The interim plan will provide an update on how project data will be collected processed managed stored during the project It will also discuss timing and conditions to eventually open the data to external organizations

Initial data management plan

The initial plan will explain how project data will be collected processed managed stored during the project It will also discuss timing and conditions to eventually open the data to external organizations

Final data management plan

The plan will report how project data are collected, processed, managed, stored during the project. It will also discuss timing and conditions to eventually open the data to external organizations also after the end of the project.

Publications

Conference proceedings (22)

ConDRust: Scalable Deterministic Concurrency from Verifiable Rust Programs

Auteurs: Felix Suchert, Lisza Zeidler, Jeronimo Castrillon, Sebastian Ertel
Publié dans: Proceedings of 37th European Conference on Object-Oriented Programming (ECOOP 2023), Numéro 263, 2023
Éditeur: Schloss Dagstuhl – Leibniz-Zentrum für Informatik
DOI: 10.4230/lipics.ecoop.2023.33

Dynamic Network selection for the Object Detection task: why it matters and what we (didn't) achieve

Auteurs: Emanuele Vitali, Anton Lokhmoto, Gianluca Palermo
Publié dans: International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS XXI), 2021
Éditeur: Springer

High-Level Synthesis of Security Properties via Software-Level Abstractions

Auteurs: Christian Pilato, Francesco Regazzoni
Publié dans: Proceedings of the 1st Workshop on Languages, Tools, and Techniques for Accelerator Design (LATTE'21), 2021
Éditeur: arxiv

Modelling linear algebra kernels as polyhedral volume operations

Auteurs: Karl F. A. Friebel, Asif Ali Khan, Lorenzo Chelini, Jeronimo Castrillon
Publié dans: Proceedings of IMPACT 2023 Intro International Workshop on Polyhedral Compilation Techniques, 2024
Éditeur: HAL Open Science

Virtio-FPGA: a virtualization solution for SoC-attached FPGAs

Auteurs: A. Panagopoulou, M. Paolino and D. Raho
Publié dans: Proceedings of IEEE International Conference on Electrical Systems for Aircraft, Railway, Ship Propulsion and Road Vehicles & International Transportation Electrification Conference (ESARS-ITEC), 2023, Page(s) 1-6
Éditeur: IEEE
DOI: 10.1109/esars-itec57127.2023.10114808

SVFF: An Automated Framework for SR-IOV Virtual Function Management in FPGA Accelerated Virtualized Environments

Auteurs: S. Cirici, M. Paolino, D. Raho
Publié dans: Proceedings of International Conference on Computer, Information and Telecommunication Systems (CITS), 2023, Page(s) 1-6
Éditeur: IEEE
DOI: 10.1109/cits58301.2023.10188786

On the Limitations of Logic Locking the Approximate Circuits

Auteurs: K. Nayak, D. Upadhyaya, F. Regazzoni, I. Polian
Publié dans: Proceedings of Asian Hardware Oriented Security and Trust Symposium (AsianHOST), 2022, Page(s) 1-6
Éditeur: IEEE
DOI: 10.1109/asianhost56390.2022.10022175

Composability of Cloud Accelerators in Virtual World Simulations

Auteurs: D. Diamantopoulos, B. Ringlein, B. Weiss, M. Lantz, F. Abel
Publié dans: Proceedings of IEEE 16th International Conference on Cloud Computing (CLOUD), 2023, Page(s) 272-274
Éditeur: IEEE
DOI: 10.1109/cloud60044.2023.00038

Platform-Aware FPGA System Architecture Generation based on MLIR

Auteurs: Soldavini, Stephanie; Pilato, Christian
Publié dans: CPS Workshop 2023, 2023
Éditeur: arXiv
DOI: 10.48550/arxiv.2309.12917

Shisha: Online Scheduling of CNN Pipelines on Heterogeneous Architectures

Auteurs: Pirah Noor Soomro, Mustafa Abduljabbar, Jeronimo Castrillon, Miquel Pericàs
Publié dans: Parallel Processing and Applied Mathematics, 2023, Page(s) 249–262, ISBN 978-3-031-30441-5
Éditeur: Springer
DOI: 10.1007/978-3-031-30442-2_19

Data Under Siege: The Quest for the Optimal Convolutional Autoencoder in Side-Channel Attacks

Auteurs: D. van den Berg, T. Slooff, M. Brohet, K. Papagiannopoulos, F. Regazzoni
Publié dans: Proceedings of International Joint Conference on Neural Networks 2023 (IJCNN), 2023, Page(s) 01-09
Éditeur: IEEE
DOI: 10.1109/ijcnn54540.2023.10191779

base2: An IR for Binary Numeral Types

Auteurs: Karl F. A. Friebel, Jiahong Bi, Jeronimo Castrillon
Publié dans: Proceedings of the 13th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies (HEART '23), 2023, Page(s) 19–26
Éditeur: Association for Computing Machinery
DOI: 10.1145/3597031.3597048

Compiler Infrastructure for Specializing Domain-Specific Memory Templates

Auteurs: Stephanie Soldavini, Christian Pilato
Publié dans: Proceedings of the 1st Workshop on Languages, Tools, and Techniques for Accelerator Design (LATTE'21), 2021, Page(s) 1-2
Éditeur: arxiv

Acceleration-as-a-µService: A Cloud-native Monte-Carlo Option Pricing Engine on CPUs, GPUs and Disaggregated FPGAs

Auteurs: Dionysios Diamantopoulos, Raphael Polig, Burkhard Ringlein, Mitra Purandare, Beat Weiss, Christoph Hagleitner, Mark Lantz, François Abel
Publié dans: Proceedings of IEEE 14th International Conference on Cloud Computing (CLOUD), 2021, Page(s) 726-729, ISBN 978-1-6654-0061-9
Éditeur: IEEE
DOI: 10.1109/cloud53861.2021.00096

Higher-Level Synthesis: experimenting with MLIRpolyhedral representations for accelerator design

Auteurs: S. Curzel, S. Jovic, M. Fiorito, A. Tumeo, F. Ferrandi
Publié dans: IMPACT 2022: The 12th International Workshop on Polyhedral Compilation Techniques, 2022
Éditeur: IMPACT

EVEREST: A design environment for extreme-scale big data analytics on heterogeneous platforms

Auteurs: Christian Pilato, Stanislav Bohm, Fabien Brocheton, Jeronimo Castrillon, Riccardo Cevasco, Vojtech Cima, Radim Cmar, Dionysios Diamantopoulos, Fabrizio Ferrandi, Jan Martinovic, Gianluca Palermo, Michele Paolino, Antonio Parodi, Lorenzo Pittaluga, Daniel Raho, Francesco Regazzoni, Katerina Slaninova, Christoph Hagleitner
Publié dans: 2021 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2021, Page(s) 1320-1325, ISBN 978-3-9819263-5-4
Éditeur: IEEE
DOI: 10.23919/date51398.2021.9473940

From Domain-Specific Languages to Memory-Optimized Accelerators for Fluid Dynamics

Auteurs: F. A. Karl Friebel, Stephanie Soldavini, Gerald Hempel, Christian Pilato, Jeronimo Castrillon
Publié dans: 2021 IEEE International Conference on Cluster Computing (CLUSTER), 2021, Page(s) 759-766, ISBN 978-1-7281-9666-4
Éditeur: IEEE
DOI: 10.1109/cluster48925.2021.00112

DOSA: Organic Compilation for Neural Network Inference on Distributed FPGAs

Auteurs: B. Ringlein, F. Abel, D. Diamantopoulos, B. Weiss, C. Hagleitner, D. Fey
Publié dans: Proceedings of IEEE International Conference on Edge Computing and Communications (EDGE) 2023, 2023, Page(s) 43-50, ISBN 979-8-3503-0484-8
Éditeur: IEEE
DOI: 10.1109/edge60047.2023.00019

STAMP-Rust: Language and Performance Comparison to C on Transactional Benchmarks

Auteurs: Suchert, F., Castrillon, J.
Publié dans: Benchmarking, Measuring, and Optimizing. Bench 2022., 2023, Page(s) 160–175
Éditeur: Springer
DOI: 10.1007/978-3-031-31180-2_10

Iris: Automatic Generation of Efficient Data Layouts for High Bandwidth Utilization

Auteurs: Stephanie Soldavini, Donatella Sciuto, Christian Pilato
Publié dans: Proceedings of ASPDAC '23: Proceedings of the 28th Asia and South Pacific Design Automation Conference, 2023, Page(s) 172–177
Éditeur: ACM
DOI: 10.1145/3566097.3567892

VOSySmonitoRV: a mixed-criticality solution on Linux-capable RISC-V platforms

Auteurs: Flavia Caforio, Pierpaolo Iannicelli, Michele Paolino, Daniel Raho
Publié dans: 2021 10th Mediterranean Conference on Embedded Computing (MECO), 2021, Page(s) 1-4, ISBN 978-1-6654-3912-1
Éditeur: IEEE
DOI: 10.1109/meco52532.2021.9460246

A System Development Kit for Big Data Applications on FPGA-based Clusters: The EVEREST Approach

Auteurs: Christian Pilato, Subhadeep Banik, Jakub Beranek, Fabien Brocheton, Jeronimo Castrillon, Riccardo Cevasco, Radim Cmar, Serena Curzel, Fabrizio Ferrandi, Karl F. A. Friebel, Antonella Galizia, Matteo Grasso, Paulo Silva, Jan Martinovic, Gianluca Palermo, Michele Paolino, Andrea Parodi, Antonio Parodi, Fabio Pintus, Raphael Polig, David Poulet, Francesco Regazzoni, Burkhard Ringlein, Roberto Rocco,
Publié dans: Proceedings of Design, Automation and Test in Europe Conference 2024, 2024
Éditeur: arXiv
DOI: 10.48550/arxiv.2402.12612

Book chapters (2)

Efficient and Secure Encryption for FPGAs in the Cloud

Auteurs: Subhadeep Banik, Francesco Regazzoni
Publié dans: Security of FPGA-Accelerated Cloud Computing Environments, 2024, Page(s) 57–80, ISBN 978-3-031-45394-6
Éditeur: Springer Nature
DOI: 10.1007/978-3-031-45395-3_3

Practical Implementations of Remote Power Side-Channel and Fault-Injection Attacks on Multitenant FPGAs

Auteurs: Dina G. Mahmoud, Ognjen Glamočanin, Francesco Regazzoni, Mirjana Stojilović
Publié dans: Security of FPGA-Accelerated Cloud Computing Environments, 2023, Page(s) 101–135, ISBN 978-3-031-45394-6
Éditeur: Springer Nature
DOI: 10.1007/978-3-031-45395-3_5

Peer reviewed articles (8)

Advancing Compilation of DNNs for FPGAs Using Operation Set Architectures

Auteurs: B. Ringlein, F. Abel, D. Diamantopoulos, B. Weiss, C. Hagleitner, D. Fey
Publié dans: IEEE Computer Architecture Letters, Numéro 22(1), 2023, Page(s) 9-12, ISSN 1556-6064
Éditeur: IEEE Computer Architecture Letters
DOI: 10.1109/lca.2022.3227643

A Survey on Domain-Specific Memory Architectures

Auteurs: Stephanie Soldavini, Christian Pilato
Publié dans: Journal of Integrated Circuits and Systems, Numéro 16/2, 2021, Page(s) 1-9, ISSN 1807-1953
Éditeur: Springer Verlag
DOI: 10.29292/jics.v16i2.509

Automatic Creation of High-Bandwidth Memory Architectures from Domain-Specific Languages: The Case of Computational Fluid Dynamics

Auteurs: Stephanie Soldavini, Karl F. A. Friebel, Mattia Tibaldi, Gerald Hempel, Jeronimo Castrillon, Christian Pilato
Publié dans: ACM Transactions on Reconfigurable Technology and Systems, 2023, ISSN 1936-7406
Éditeur: Association for Computing Machinery (ACM)
DOI: 10.1145/3563553

Compact Circuits for Efficient Möbius Transform

Auteurs: Banik, S., Regazzoni, F.
Publié dans: IACR Transactions on Cryptographic Hardware and Embedded Systems, Numéro 2024(2), 2024, Page(s) 481–521, ISSN 2569-2925
Éditeur: IACR
DOI: 10.46586/tches.v2024.i2.481-521

Dynamically-Tunable Dataflow Architectures Based on Markov Queuing Models

Auteurs: Tibaldi, M.; Palermo, G.; Pilato, C.
Publié dans: MDPI Electronics, Numéro 11/4, 2022, ISSN 2079-9292
Éditeur: MDPI
DOI: 10.3390/electronics11040555

The Side-Channel Metric Cheat Sheet

Auteurs: Kostas Papagiannopoulos, Ognjen Glamočanin, Melissa Azouaoui, Dorian Ros, Francesco Regazzoni, and Mirjana Stojilović
Publié dans: ACM Computing Surveys, Numéro 55(10), 2023, Page(s) 1–38, ISSN 0360-0300
Éditeur: Association for Computing Machinary, Inc.
DOI: 10.1145/3565571

Generating Posit-based Accelerators with High-Level Synthesis

Auteurs: R. Murillo, A. A. D. Barrio, G. Botella, C. Pilato
Publié dans: IEEE Transactions on Circuits and Systems I: Regular Papers, 2023, ISSN 1549-8328
Éditeur: Institute of Electrical and Electronics Engineers
DOI: 10.1109/tcsi.2023.3299009

A Survey of FPGA Optimization Methods for Data Center Energy Efficiency

Auteurs: M. Tibaldi, C. Pilato
Publié dans: IEEE Transactions on Sustainable Computing, 2023, ISSN 2377-3782
Éditeur: IEEE
DOI: 10.1109/tsusc.2023.3273852

Other (3)

Poster: MLIR Loop Optimizations for High-Level Synthesis: A Case Study

Auteurs: Serena Curzel, Sofija Jovic, Michele Fiorito, Antonino Tumeo, Fabrizio Ferrandi
Publié dans: In Proceedings of the International Conference on Parallel Architectures and Compilation Techniques (PACT '22), 2023, Page(s) 544–545
Éditeur: Association for Computing Machinery
DOI: 10.1145/3559009.3569688

Etna: MLIR-Based System-Level Design and Optimization for Transparent Application Execution on CPU-FPGA Nodes

Auteurs: Stephanie Soldavini, Felix Suchert†, Serena Curzel, Michele Fiorito, Karl Friebel, Fabrizio Ferrandi, Radim Cmar, Jeronimo Castrillon, Christian Pilato
Publié dans: Proceedings of IEEE Symposium on Field-Programmable Custom Computing Machines FCCM 2024, 2024
Éditeur: IEEE

Poster: Anomaly detection to improve security of big data analytics

Auteurs: Tom Slooff, Francesco Regazzoni, Fabien Brocheton, Antonio Parodi, Radim Cmar
Publié dans: Proceedings of the 19th ACM International Conference on Computing Frontiers (CF '22), 2022, Page(s) 205–206
Éditeur: Association for Computing Machinery
DOI: 10.1145/3528416.3530868