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Parallel Associative Development Machine as a Vehicle for Artificial Intelligence

Objective

The objective of PADMAVATI was to develop a high-performance computer system suitable for symbolic and time-critical applications such as real-time speech and image understanding.
The machine architecture is based on an array of computational transputer nodes, each containing a high-performance multiprocessor and memory and communication interfaces. The use of an associative memory architecture (hashed DRAM and a CAM) accelerates the programming languages and applications. The programming environment was standard Prolog and LE-LISP with extensions to support parallel execution. The complete machine has been tested by implementing experimental, computationally-intensive tasks from the fields of parallel expert systems, speech, and image understanding.
The objective was to develop a high performance computer system suitable for symbolic and time critical applications such as real time speech and image understanding. The machine architecture is based on an array of computational transputer nodes, each containing a high performance multiprocessor and memory and communication interfaces. The use of an associative memory architecture (hashed dynamic and random access memory (DRAM) and a content addressable memory (CAM)) accelerates the programming languages and applications. The programming environment was standard Prolog and LE-LISP with extensions to support parallel execution. The complete machine has been tested by implementing experimental, computationally intensive tasks from the fields of parallel expert systems, speech, and image understanding. Processor nodes were built, and tested. The associative memory (CAM) chips have been designed and built, and are being packaged using TAB bonding. A message passing run time system was developed, to support communication in the network. The symbolic languages LE-LISP and Prolog were extended to exploit the architecture and allow macro parallelism (the code is annotated by the user when parallelism is required). A micro parallel Prolog, LOGARITHM, was developed. Three prototypes, comprising 16 nodes with a reconfigurable network and 1 to 16 CAMs have been integrated.
DYNET, a dynamically reconfigurable and cascadable routing chip, is now available as a commercial product. It allows up to 256 nodes to be connected in the desired network topology.
Processor nodes (a T800 transputer and CAM with 8 or 16 Mbytes of DRAM) were built, and tested. The associative memory (CAM) chips have been designed and built, and are being packaged using TAB bonding. The CAM can be seen either as an intelligent memory with a constant-time search with "don't cares", or alternatively as a SIMD processor array.
A message-passing run time system was developed, to support communication in the network.
The symbolic languages LE-LISP and PROLOG were extended to exploit the architecture and allow macro-parallelism (the code is annotated by the user when parallelism is required). A micro-parallel Prolog, LOGARITHM, was developed as well.
Three prototypes, comprising 16 nodes with a reconfigurable network and one to sixteen CAMS have been integrated.
Exploitation
Many applications can be envisaged for the state-of-the-art CAM. The viability of associative devices in an efficient implementation of concurrent LISP and sequential and parallel Prolog have been demonstrated.
By allowing physically distant nodes to communicate directly, DYNET allows users to integrate now functionalities that will be available in the next-generation transputer; users can explore this new functionality before the new transputer becomes available.

Coordinator

THOMSON CSF
Address
160 Boulevard De Valmy
92074 Paris La Defense
France

Participants (3)

Centro Studi e Laboratori Telecomunicazioni SpA
Italy
Address
Via G. Reiss Romoli, 274
10148 Torino
FIRST INTERNATIONAL
Greece
GEC-Marconi Materials Technology Ltd
United Kingdom
Address
Elstree Way
WD6 1RX Borehamwood