Manufacture and property measurements of silicon/glass layer/silicon wafer bonding.
Substantial reduction of the thickness of the sputtered Corning 7740 bond glass layer and a low anodic voltage have been obtained. The silicon/glass water anodic bonding is completed and well established.
A very reliable shear test method was developed to determine the fracture resistance of the bonding zone. A Weibull analysis was used for describing quantitative the distribution of the bonding strengths and fracture characteristics. A fracture mechanics-based methodology has been proposed and calibrated numerically to predict the limiting conditions under which Si wafer-glass-Si wafer bonded systems widely used in microsensor applications will fail by interfacial debonding from either edge defects or microflows.
The mechanical tests showed a very high tensile yield stress which is at least as high as that of Si/pyrex/Si bond.
A relation has been proposed which gives the fracture strength of the bond (or critical energy release rate for interface failure) in terms of the thickness of the bond, the substrate elastic properties, the polymer yield strength, and a proportionality constant which is calibrated numerically.
Thick layers can be structured to form flow channels in interconnecting levels in microfluidic systems.
Polysiloxane has been chosen as base material, due to its excellent mechanical parameters, its chemical stability and its proven biocompatibility. The polymerisation parameters and the resulting mechanical parameters of the polymer can be adjusted to the desired application. The great advantage of this method is that the bonding is performed at room temperature and low contact pressure.
An assembly process of chips or sensors on silicon substrates involving electrical connections and hermetic sealings has been developed. This wafer scale silicon-metal-silicon assembly is based on a flip-chip bonding technique using solder bumps.
The process fabrication of the soldering bumps located on the chips was optimized. The assembly of the two wafers (one wafers containing the chips and one wafer containing the substrates) was realised by using a commercial flip-chip aligner bonder.
Four technology demonstrators were produced.
The objective of this project is to develop flexible process technologies for the assembly of microsensors susteùs p, a somocp,-wafer scale. Particular attention is give to packaging and bonding techniques. Maximum compatibility with IC processes is pursued. Design rules for reliability-based design optimization are developed. Major tasks are:
(i) development of Si/glass layer/Si bonding
(ii) development of Si/polymer/Si bonding
(iii) assessment of bonding integrity
(v) fabrication of demonstrators, testing the integrated system
(vi) development of unified design methodology for microsystems
Results should provide a sound technological bse for high volume, low cost manufacturing of microsensors and microsystems. The resulting design guidelines are a prerequisite for future development of Application Specific Integrated Systems (ASIS).
Funding SchemeCSC - Cost-sharing contracts
KT18 5BW Epsom