The aim of this project is to improve our understanding of the reliability problem in submicrometer bipolar transistors for BiCMOS technologies and in 0.251fm gate-length CMOS technologies. The work will focus on the hot-carrier effects. Extensive experimental studies covering various stressing conditions with various post-stress thermal annealing and bias treatments (i.s.o.) should be carried out on high performance bipolar devices which are assumed to be integrated into a 0.51fm CMOS process. An important goal is to extract by experiments and modelling the amount, nature and location of interface traps and oxide-trapped charge produced in electrical stress. The possibility to employ charge-pumping measures for this problem will be investigated. The study should be strongly supported by numerical modelling of the conditions applicable to the interior of devices at the stress bias and of the impact of the damage on the device characteristics. Software tools necessary to accomplish this task should be developed (using the present simulators e.g. MINIMOS6 as a base). T. complementary experimental and modelling approach should result in the development of time prediction models for submicrometer bipolar devices operating in DC and AC conditions which is the main goal of this project.