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Design of an interface ASIC for RISC systems using a VHDL based "independent" environment

Objective

- The adoption of an advanced design methodology with the use of VHDL and the design of an interface ASIC for the R4000 RISC family of IDT microprocessors. MLS plans to design this ASIC in collaboration with the Centre of Microelectronics of INTRACOM (CEM). CEM will provide the advanced design practice, the training of MLS engineers, the final Mentor Graphics platform environment and will do the final technology choice as well as supporting the implementation of the ASIC.

- To strengthen MLS' position in the embedded control systems market and in the prototype development work.

- To disseminate the results of this Application Experiment on a European-wide scale.

This Application Experiment has as its main objectives the utilisation of VHDL, the use of an "Independent" Environment and the adoption of an advanced design methodology in order to improve the standard of design practice currently used by MLS Firmware S.A (OrCAD & ViewLogic EDA Tools).
The Application Experiment will focus on the design of an advanced interface ASIC for the R4000 RISC family of IDT microprocessors that is used in high-performance embedded control systems i.e. fast telecommunications switching, high-speed networking (ATM switches) etc. The product will be tested with advanced prototype testing methods. The ASIC design will be carried out by MLS engineers with the support of INTRACOM engineers to ensure that the end-user learns sufficiently to repeat the process in the future without support.

Coordinator

Mls Firmware
Address
Alex. Papanastasiou St. 34
54639 Thessaloniki
Greece