Objective
Reduction of manual overhead in coverage analysis to 25% of its current value.
Reduction of machine time to perform VHDL statement coverage to 75% of current value.
Add ability to generate branch, condition, path triggering and signal coverage to existing ability.
This Application Experiment will measurably improve the efficiency and quality of functional fault coverage of highly complex systems on Silicon. The VHDL Cover tool will be integrated into the existing design flow. The tool will be exercised and evaluated during application to the design of the Chameleon family of 64-bit microprocessors offering highly integrated software-based solutions thereby supporting flexibility in the end application.
Functional verification is estimated to take between 30 and 50% of the design resource for typical microprocessor development. The expected impact from the experiment will be improvements in the efficiency and quality of functional coverage of these highly complex systems on Silicon.
Fields of science (EuroSciVoc)
CORDIS classifies projects with EuroSciVoc, a multilingual taxonomy of fields of science, through a semi-automatic process based on NLP techniques.
CORDIS classifies projects with EuroSciVoc, a multilingual taxonomy of fields of science, through a semi-automatic process based on NLP techniques.
- engineering and technologyelectrical engineering, electronic engineering, information engineeringelectronic engineeringcomputer hardwarecomputer processors
- natural scienceschemical sciencesinorganic chemistrymetalloids
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Call for proposal
Data not availableFunding Scheme
ACM - Preparatory, accompanying and support measuresCoordinator
BS12 4SQ Almondsbury
United Kingdom