Objective
Our long term objectives are :
- to develop high resolution nanofabrication of coupled islands for single electron electronics, with potential for mass fabrication .
- to form a sound basis and pave the way for new generations of solid-state memories with terabit storage capacity, with appropriate access speed and full compatibility with mainstream silicon technology
The objectives of the FASEM programme were to develop techniques for the high-resolution nanofabrication of coupled islands for single-electron devices and to use this technology as a basis for a new generation of silicon-compatible solid-state memories with terabit potential.
The consortium has invented a silicon-based single-electron memory cell: the Lateral Single-Electron Memory (L-SEM). The L-SEM can be used to fabricate a fast, random-access memory with the potential for large-scale integration. The L-SEM cell uses a single-electron device coupled to a conventional MOSFET. The cell has been fabricated in crystalline silicon-on-insulator (SOI) material using a heavily-doped, side-gated silicon nanowire single-electron transistor (SET). Typically, the SET silicon nanowire cross-sectional area is less than ~40 nm (40 nm. The cell has been operated with detectable storage of small electron numbers (~60 electrons on a 1 µm (70 nm area memory node). The write/erase time of the cell is 10 ns and the cell can operate successfully at temperatures up to circa 50 K. The crystalline silicon-on-insulator L-SEM cell has been integrated into a small 3 (3 bit memory array. Full functional operation of the memory has been demonstrated, including the read/write timing cycle and cell selection without data corruption.
The side-gated silicon nanowire SET has also been fabricated in polycrystalline silicon films, but not yet integrated into a memory cell. In addition, an alternative SET design using a single silicon island has been demonstrated in crystalline silicon-on-insulator material and has been directly incorporated into the L-SEM. The silicon island in these devices can be doped or undoped, with dimensions as small as 20 nm. A different approach to single-electron transistors, based on sub-5 nm diameter metallic islands has also been developed and single-electron effects observed up to room temperature. This type of Coulomb blockade structure is also capable of being incorporated in a variant of the L-SEM cell that may operate at high temperatures tending towards room temperature, but this has yet to be demonstrated.
A parallel approach to the high-speed volatile L-SEM has also been investigated. A new dynamic memory cell using a two-dimensional array of silicon nanocrystals for information storage has been demonstrated. The nanocrystals were fabricated by very-low energy Si+ ion implantation and subsequent thermal annealing in the gate oxide of a conventional MOSFET, and located at a tunnelling distance (< 2 n) from the channel. The multi-nanocrystal floating-gate MOSFET device operates at room temperature and exhibits high endurance and write/erase times as fast as 50 nm which approach those of conventional DRAM.
The material used for much of the research was state-of-the-art bonded SOI material with ultra-thin layers of oxide (~40 nm-thick) and silicon (~40 nm-thick). This project has advanced the specification of bonded SOI material available for research.
The experimental programme has been strongly supported by modelling and simulation of the silicon SETs, the L-SEM cell and the metallic SETs. Novel means of metallic dot deposition and control, by evaporation of ion sources as well as STM- and AFM-assisted lithography, were also investigated and used to create SETs. Throughout the programme, the compatibility of the designs with CMOS circuitry and processes was ensured. Part-processed circuits using both crystalline silicon and polycrystalline silicon formed the basis of the research. New silicon device and circuit processes compatible not only with SOI material but also with silicon SETs and metallic SETs were developed during the course of the FASEM project.
The project has been successful in showing that single-electron transistors can be the basis of a CMOS-compatible memory technology for the terabit era. The fabrication of nanostructures for these devices has advanced the state-of-the-art significantly, and small L-SEM memory arrays have been linked to peripheral devices in a CMOS circuit, establishing the feasibility of the single-electron memory in silicon.
The results of the project will provide information on the feasibility of using single electron charging effects as the basis for a future memory technology. The research will also advance nanofabrication technology and nano-scale processing technology for semiconductor devices.The architecture will be developed while taking into account the strengths and weaknesses of single electron devices. New concepts will need to be realised for inter-connected devices and circuits, and methods for low power coupling between devices as well as between SETS and CMOS will be researched.
The basic SETS will require a fabrication strategy for metallic and semiconductor based devices. These will take into account the need to develop strategies which will eventually lead to practical production methods. Low power consumption in the circuits will be of prime importance, but attempts will also be made to raise the operating temperature of the SETS to levels which are significantly higher than 4.2K and possibly room temperature. Towards the conclusion of the project, primitive memory circuits based on SETs will be realised and their performance will be compared to CMOS circuits. Throughout the project experimental work will be strongly supported by the simulation of device structures and the fabrication will be optimised on the basis of the guidance received. Simulation will also support electrical properties of SETS and memory devices. The simulation will be based on an in-depth understanding of the physics underlying the Coulomb blockade effect and is likely to be a vital requirement.
Pushing the nanofabrication methods to the sub-50nm level with a good control of regularity and created defects, and explore the feasibility of mass nanofabrication will benefit to any field relevant to ultra-high resolution nanofabrication: single electron electronics, photonics, nanomagnetism...
The benefits of making SET memories are the reduced size of the individual memory cells, the reduced power consumption and the possibility to integrate them with Si logic. A memory cell has only two requirements : 1) that its state can be changed to represent a <<1 >> or <<0>>, and 2) that its state can be sensed. With SET memories this could be accomplished with the movement of a single electron. For today's DRAMs this is done by charging and discharging a capacitor. With SETs a chip of one terabit capacity would not exceed a few cm2.
In very special applications, single-electron memory could be used in commercial products within 10 years. More general applications could be expected by the year 2015 as predicted by the trend curves of semiconductor memory technology. This project offers a real prospect for commercial exploitation in 10 to 15 years if the research is successfully carried out.
Fields of science (EuroSciVoc)
CORDIS classifies projects with EuroSciVoc, a multilingual taxonomy of fields of science, through a semi-automatic process based on NLP techniques. See: The European Science Vocabulary.
CORDIS classifies projects with EuroSciVoc, a multilingual taxonomy of fields of science, through a semi-automatic process based on NLP techniques. See: The European Science Vocabulary.
- engineering and technology nanotechnology nano-materials nanocrystals
- natural sciences physical sciences electromagnetism and electronics semiconductivity
- natural sciences chemical sciences inorganic chemistry metalloids
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Keywords
Project’s keywords as indicated by the project coordinator. Not to be confused with the EuroSciVoc taxonomy (Fields of science)
Project’s keywords as indicated by the project coordinator. Not to be confused with the EuroSciVoc taxonomy (Fields of science)
Programme(s)
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Multi-annual funding programmes that define the EU’s priorities for research and innovation.
Topic(s)
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Calls for proposals are divided into topics. A topic defines a specific subject or area for which applicants can submit proposals. The description of a topic comprises its specific scope and the expected impact of the funded project.
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Funding Scheme
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Funding scheme (or “Type of Action”) inside a programme with common features. It specifies: the scope of what is funded; the reimbursement rate; specific evaluation criteria to qualify for funding; and the use of simplified forms of costs like lump sums.
Coordinator
92195 Meudon
France
The total costs incurred by this organisation to participate in the project, including direct and indirect costs. This amount is a subset of the overall project budget.