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Mapping for Low Power

Objective



The project will allow the continuation of cooperation started during the ESPRIT BRA LINK (6855) project on links between low-level and high-level synthesis, among three partners of this project: UCL and INPG from the EU and ICI from Moscow, RU.
The three partners have already developed basic and efficient tools in digital logic synthesis. They were working together on low level synthesis CAD tools for logic synthesis, principally based on Boolean and BDD techniques. The research efforts will continue this action in the improvement of algorithms for low power efficient VLSI systems, principally in the context of the technology mapping.
The main topics covered will be the enhancement of efficient decomposition techniques for low power, the development of new covering and matching algorithms, and critical path detection and remapping in close relation to place and route tools.
All the efforts will lead to coherent CAD developments which will be tested on realistic system designs. The requested contribution is to help in regular contacts of ICI with the EU partners and to open ICI to the research community of the European Union countries. This will enable them to access and be trained to efficient CAD tools. Joint publications and presentations at international conferences and workshops are planned, and a final workshop on efficient low power VLSI systems will conclude the project.

Funding Scheme

ACM - Preparatory, accompanying and support measures

Coordinator

UNIVERSITE CATHOLIQUE DE LOUVAIN
Address
Place De L'universite 1
Louvain-la-neuve
Belgium

Participants (2)

INSTITUT NATIONAL POLYTECHNIQUE DE GRENOBLE
France
Address
46,Avenue Felix Viallet
38031 Grenoble
INTERNATIONAL COMPUTER INITIATIVE SCIENTIFIC CENTER
Russia
Address

103498 Moscow K-498