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Content archived on 2024-05-15

Local Integrated Direct Chip Attach Technology


A new "graded build-up" technology for PCBs will be established, to cope with chip I/O pad pitches of 50 µm, either flip chipped or wirebonded, and to handle routing and placement of dense area array packages (CSP). The top layers on the build-up stack will have track width and spacing of 25 µm, and 25 µm microvias. Laser structuring will be the key issue of the technology, but also other processes will change accordingly, as will do CAD tooling and electrical testing. The developed board technology will e validated by making mixed assemblies of advanced, fine pitch packages and naked dice, together with SMD packages. Test vehicles for the technology development will be fully characterized and checked for reliability. A final demonstrator in the area of portable telecom products will show the full possibilities of the technology.

The LIDCAT project has as a major objective, to establish a fine-line technology on printed circuit board, with 25 µm track width and spaces, and 25 µm microvias, as a "graded build-up" from core multilayer to the fine pitch top-assembly layer. The board will then be compatible with fine pitch (50 µm) naked dice for flip-chip or wirebonding and will have an enhanced routability for dense area array packages (µBGA, CSP). Compatibility will be provided with SMD technology, and new Pb-free solder technique or adhesives. Laser structuring techniques (in resist or thin metals) will be introduced in the process and all process steps will be reviewed to be compatible with the fine pitch. During development of this new technology CAD tools, and tools for testing the boards will be reviewed. A validation of the technology is foreseen by means of a telecom demonstrator. The objectives in this project are meeting the roadmaps of European (and worldwide) OEM's.

Work description:
The project is divided into 6 workpackages. Each of them is addressing a specific need in the technology development. In WP1 general specifications for the demonstrator and related products are defined and translated to technology specifications. The bulk of the work has to be done in WP2 (board technology), where the process for the new "graded build-up" technology will be developed. An initial study on base material will allow to choose the best materials available at the moment of the project. Different laser systems (available at the moment of the project. Different laser systems (available inside and outside the consortium) and processes will be explored. For the development of a graded build-up technology, much effort will be put in new board processes, not only by introducing new techniques like laser direct writing or laser structuring of etch resists, but also by optimising all basic build-up processes to the targeted fine features. The consortium has also chosen for an integrated approach by involving CAD design and testing methods in the development. The LIDCAT technology will further be used for mixed assembly tests in WP3. Different types of test chips, in bare die form or packaged in a variety of fine pitch and area array packages will be provided. Technical items in assembly will be the use of Pb-free solder and/or adhesive technology, and COB with flip chip or wirebonding. Boards and finished assemblies will be fully characterised and tested on reliability.
An important aspect of the project is the validation of the developed technologies in a demonstrator. This demonstrator is situated in the area of mobile phones, and will thus profit the most from space saving, increased functionality, lighter weight, etc. It will also allow to do cost calculations in a real environment, and to extrapolate the possibilities of the technologies towards exploitation in Europe. A last workpackage is dealing with the project management, which is seen as an important tool to achieve the milestones and deliverables of the project.

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Participants (4)