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Content archived on 2024-05-27

Mechanical stress model for packaged ICs


The primary objective of the MESMERIC project is to produce a standard silicon test chip, which can be used to:
(a) Characterise current/future microelectronics/optoelectronics packages and
(b) validate thermal/mechanical models of packages.

This chip will be fabricated on a standard foundry process, and thus will be easily available at minimum cost. Users will be able to verify their FE models by comparing the modelled results with measured results obtained directly from the test chip. Thus, it meets the aims of Key Action IV.8,1 & IV.8.4 by allowing users to rapidly adopt thermo-mechanical modelling techniques due to the availability of a standard and proven European test chip. This project addresses specific areas of concern in the Community, relating to access, ease of use, cost-effectiveness and standardisation. It will provide a generic test capable of meeting all thermo-mechanical measurement needs across a wide range of package types. A feature of the project will be the innovative circuit features strain gauge characterisation methods and compact, user-friendly test hardware/software.

These are 8 key objectives of the MESMERIC project:
- Provision of a standard, easily available and cost effective test chip to European users.
- Provision of on-chip PROM and decoder circuitry to give automatic traceability of individual die.
- Provide a PC-compatible desktop interface unit, to give a convenient, small footprint test capability that does not require scarce laboratory or production resources,
- Provide strain gauges, heaters and temperature measurement capability.
- Provide size flexibility to allow the test chip to be used in a wide range of package sizes,
- Detailed mapping of the stresses on the silicon surface will be provided by arraying a large number of gauges across the silicon surface and addressing them by a multiplexing/decoding circuit.
- Ensure ease of use by automated collection and analysis of test chip results.

This will allow a user to place a component in a socket and run the analysis routine provided with the PC interface.
- Provide ongoing expertise and support to MESIERIC users.

Work description:
The work will be organised around the achievement of a number of milestones as follows:
- T1 Identify the test chip requirements and create a design floor plan. This involves a comprehensive literature review and a review of existing test chip experience among the project partners. The objective is to identify the required features and create a draft floorplan. The test hardware and software requirements are also identified.
-T2.1 Detailed design of the test chip. This activity covers the circuit design and its detailed layout. From this, the masks necessary for T2.2 are created.
-T2.2 Fabrication of the test chip. A unique CAM process flow is created for the test chip, detailing the process steps etc. When this is in place, the wafers can be started to verify silicon functionality. A test programme will be written in order to allow a wafer prober to individually check each die on the wafer and then read and store the strain gauge data against the appropriate die number as read from the PROM circuit.
-T3 Test chip characterization. A new 4-point strain gauge calibration fixture will be developed to enable more gauges to be simultaneously calibrated. A further fixture will be developed to simulate compressive loading. Heaters and temperature measurement diodes will also be characterised.
-T4 Develop model with which to compare test chip data. A new sequential process model will be developed in order to ascertain whether current assumptions that die are in a "zero stress" date prior to packaging, are correct. In addition, package models will be created for later comparison with actual measured data from the test itself
-T5.1 Hardware development. This will consist of the development of the PC interface to allow testing to take place
-T5.2 Software development. This software will be designed to automate the data collection and analysis process. It will be targeted at a "plug and play" mode of operation.
-T6 Validate test chip performance in silicon and compare with modelled results. Test chips will be assembled in a number of package types and measured data compared with that from the FE models created in T4 above.
-T7 Exploitation and dissemination. The project partners will ensure that potential users have access to the silicon, hardware/software, project findings and manuals. This will be done by creating a project website, a users manual, presenting papers and providing ongoing consultancy.

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Participants (4)