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Automatic Tool For Insertion And Simulation Of Fault Tolerant Architectures

Objective

Fault-Tolerant circuits are currently required in several major application sectors. Although the particular circuit structures that allow the building of an FT circuit have been studied in the past, currently there is a lack of CAD support in the design and evaluation of FT circuits. As a consequence, these tasks have to be carried out manually and result in reduced productivity, reliability and efficiency. The aim of the AMATISTA project is to develop a set of tools devoted to the design of FT digital circuits. The toolset is composed of: an automatic FT insertion tool and a simulation tool to validate the FT designs. The toolset will take a technology-independent approach based on RT-level VHDL. It will be first integrated in the current design flow of automotive and aerospace companies. The quantitative and qualitative results of this project will be illustrated by two industrial demonstrations in the areas mentioned above.

Objectives:
The primary objective of project AMATISTA is to provide a modern solution to the design of fault-tolerant circuits. This solution is aimed at improving the design flow for this type of circuits in order to achieve the following primary goals:

Increase design productivity
Enhance circuit reliability.
Simplify introduction of the technology into current design environments.
To achieve these goals, the project focuses on delivering a commercial fault-tolerant design toolset that will consists of:

An automatic fault tolerant insertion tool.
A simulation tool to validate the fault-tolerance of the designs.
The toolset will be integrated in the current fault tolerant design flow of two industrial companies (from the automotive and aerospace sectors). By using some real applications, the new design flows will be explored, and analysed quantitatively and qualitatively. The resulting toolset will be commercially exploited in a variety of sectors within the growing industrial community concerned about reliability issues.

Work description:
The project is divided into three main phases:

Specification. The industrial partners describe their fault tolerant problems and their current FT design flows. Possible optimisations, enhancements and future needs will be also clearly identified. Then the FT toolset will be fully specified (T0=>T0+6).

Development: The toolset will be developed according to the specifications. A Beta release of the program will be shipped at month 18. (T0+6 => T0+18)
Demonstration and Tool Engineering: The industrial partners will develop examples and evaluate the toolset in their application domains. They will provide feedback in order to enhance and debug the toolset. At the same time, the toolset will be engineered in order to obtain commercial quality tools. (T0+2 => T0+24).

Funding Scheme

CSC - Cost-sharing contracts

Coordinator

ALCATEL ESPACIO SA
Address
Calle Einstein 7
28760 Tres Cantos - Madrid
Spain

Participants (4)

CENTRO RICERCHE FIAT SOCIETA CONSORTILE PER AZIONI
Italy
Address
Strada Torino 50
10043 Orbassano (To)
FTL SYSTEMS UK LIMITED
United Kingdom
Address
2 Venture Road, Chilworth Science Park
SO16 7NP Chilworth, Southampton
POLITECNICO DI TORINO
Italy
Address
Corso Duca Degli Abruzzi 24
10129 Torino
UNIVERSIDAD CARLOS III DE MADRID
Spain
Address
Calle Madrid 126
28903 Getafe (Madrid)