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DYNAMIC IMAGE COMPUTING USING TERA-SPEED ANALOGIC VISUAL MICROPROCESSORS

Objective

DICTAM aims to produce a new class of image-processing systems based on an optimum, adaptive synergy of Analog Programmable Array Processors (APAPs) and conventional DSPs, including concurrent image transduction and processing by means of Focal-Plane APAPs (FPAPAPs). Substantial advantages in computing speed, system cost, power consumption, and overall quality of the processing functions are expected. The tasks include advanced microelectronic circuit design of mixed-signal APAPs, FPAPAPs and image memory devices, development of optimum hardware/software architectures, of system-specific processing algorithms, and the integration of these basic ingredients into several demonstrators. Within the wide range of applications, the project will focus on real-time dynamic image coding, video authenticity and integrity verification, visual inspection in automated production processes, and motion picture related applications. DICTAM aims to produce a new class of image-processing systems based on an optimum, adaptive synergy of Analog Programmable Array Processors (APAPs) and conventional DSPs, including concurrent image transduction and processing by means of Focal-Plane APAPs (FPAPAPs). Substantial advantages in computing speed, system cost, power consumption, and overall quality of the processing functions are expected. The tasks include advanced microelectronic circuit design of mixed-signal APAPs, FPAPAPs and image memory devices, development of optimum hardware/software architectures, of system-specific processing algorithms, and the integration of these basic ingredients into several demonstrators. Within the wide range of applications, the project will focus on real-time dynamic image coding, video authenticity and integrity verification, visual inspection in automated production processes, and motion picture related applications.

OBJECTIVES
DICTAM's objective is to develop new processor architectures, algorithms and integrated circuits for real-time image processing, and to corroborate their advantages using programmable hardware demonstrators applied to selected real-case examples: real-time video compression, image authenticity / integrity verification, and various visual inspection and motion scene evaluation tasks. DICTAM/s success relies on three interlaced objectives:
1) Design of custom Analog Programmable Array Processors (APAPs), Focal Plane APAs (FPAPAPs), and image memory devices with optimum trade-off among area efficiency, accuracy, speed, and power consumption.
2) Development of optimum hardware / software system architectures hosting the new devices as well as conventional DSPs.
3) Development of image processing algorithms for the new processing systems, including adaptive partitioning of the processing tasks among APAPs and DSPs.

DESCRIPTION OF WORK
The technical work has been structured into four workpackages.
WP1 (Design and test of chip-sets): Development of circuit strategies for optimum trade-offs among speed, accuracy, area efficiency, And power consumption of Analog Programmable Array Processors (APAPs), Focal Plane (FPAPAPs), and image memory devices (Analog RAMs) in 0.35 um and/or 0.25um CMOS technologies. Characterisation of CMOS-compatible optical sensors and selection of an optimum alternative for FPAPAPs. Design and test of a 128 x 128 general-purpose APAP chip and 256 x 256 ARAM to be used in a video computing demonstrator. Design and test of a dedicated 128 x 128 FPAPAP CMOS chip with embedded image acquisition to be used in an intelligent visual device demonstrator.
WP2 (Design an test of Analogic Cellular Engine (ACE) boards): Specification, design and test of different hardware platforms hosting alternative combinations of the chips developed in WP1, conventional Digital Signal Processors (DSPs), and conventional image acquisition devices. Development of the software environment required for the control and optimum exploitation of the new ACE architectures. Development of learning and fault-tolerant algorithms for robust applications under the expected residual parametric errors of the analog circuitry.
WP3 (Video Computing): Development of ACE-compatible algorithms for video coding, authenticity, and integrity verification, and of higher level algorithms for selected video computing applications based on the new computing architectures.
WP4 (Embedded Intelligent Visual Devices): Specification of the FPAPAP functionality required for visual-inspection and motion-environment event detection applications. Development of algorithms for environmental surveillance, intelligent scanning, hand-held videoconference, and of higher-level algorithms for visual-inspection applications defined by industrial partners.
Three chips have been designed and tested in the course of DICTAM, called respectively ACE4k, ACE16k and CACE1k. The first was mostly designed during the first phase of the Project, while the others have been designed during the second phase. These chips, whose major features are listed below in this report, define the state-of-the-art regarding mixed-signal custom VLSI design. The chips designed within DICTAM have architectural similarities with the so-called Single Instruction Multiple Data systems although they work directly on analog signal representations, obtained through embedded optical sensors, and hence do need neither a front-end sensory plane nor analog-to-digital converters. The architecture of these visual microprocessors includes a core array of interconnected elementary processing units, surrounded by a global circuitry.

This latter circuitry is intended for: control and timing; addressing and buffering of the core cells; input/output; storage of user-selectable instructions (programs) to control the sequence of operations of the processing core; storage of user-selectable analogic programming parameter configurations (templates). On the other hand, the core of interconnected processing units embeds different functions on a common silicon substrate, namely: 2-D sensing; 2-D analog/digital array processing concurrent with the signal sensing; 2-D spatio-temporal processing determined by local, receptive-field-like programmable interconnections; 2-D memory banks for concurrent on-line up- and down-loading of short-term analog and digital data. The improvement in Hardware and Software development for this type of chips has been very important. Different system propotypes are already available where case study applications have been developed.

Funding Scheme

CSC - Cost-sharing contracts

Coordinator

CONSEJO SUPERIOR DE INVESTIGACIONES CIENTIFICAS
Address
C/ Serrano 117
28006 Madrid
Spain

Participants (6)

BARCO NV
Belgium
Address
President Kennedypark 35
8500 Kortrijk
ECOLE POLYTECHNIQUE FEDERALE DE LAUSANNE
Switzerland
Address
Ecublens
1015 Lausanne
KATHOLIEKE UNIVERSITEIT LEUVEN
Belgium
Address
Oude Markt 13
3000 Leuven
MAGYAR TUDOMANYOS AKADEMIA SZAMITASTECHNIKAI ES AUTOMATIZALASI KUTATO INTEZET
Hungary
Address
Kende U. 13-17
1111 Budapest
STMICROELECTRONICS S.R.L.
Italy
Address
Via Olivetti 2
20041 Agrate Brianza
UNIVERSITA DI CATANIA
Italy
Address
Piazza Universita 2
95124 Catania