CORDIS provides links to public deliverables and publications of HORIZON projects.
Links to deliverables and publications from FP7 projects, as well as links to some specific result types such as dataset and software, are dynamically retrieved from OpenAIRE .
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The Hash VLSI IP Module is a hardware module that performs several hashing algorithms needed for security applications. It supports SHA-1, RipeMD-160 and MD-5, SHA-256, and is prepared for including upcoming hash algorithms with bigger size (SHA-512). It includes the controlling circuits and a generic 32-bit bus interface that can be eaisly adapted to customer's needs. The Hash VLSI macro cell is developed by IAIK which owns the IPR. The Hash IP module can be used by a silicon system integrator and comes with a defined set of supported operations, functional models in C++ and VHDL, the hardware description itself, and testing strategy. The circuit architecture is designed and full-custom approaches are developed wherever useful in a way to be able to adjust the speed/area/power consumption tradeoffs according to various application's needs. For FPGA implementation, optimized versions are available for SHA-1 and SHA-256.
The AES IP module is a hardware module that performs symmetric encryption and decryption according to the AES algorithm (Rijndael). The IAIK AES module is designed with special emphasis on low area and low energy consumption, without reduction of security. It supports AES encryption and decryption in ECB and CBC mode of operations. A unit for setting up the AES key, the controlling circuits and an AMBA interface is also part of the module.
The AES module is available in different versions, to provide minimal area and energy consumption for given performance values. The full version supports the full AES standard (all specified key-lengths).
The bus interface can be changed easily to customers needs in order to incorporate the AES module into systems on chip which need AES support in hardware for reasons of encryption speed and higher energy efficiency. The AES module is developed by IAIK which owns the IPR. The AES IP module can be used by a silicon system integrator and comes with a defined set of supported operations, functional models in C++ and VHDL, the hardware description itself, and testing strategy. The circuit architecture is designed and full-custom approaches are developed wherever useful in a way to be able to adjust the speed/area/power consumption tradeoffs according to various applications' needs. Additional to the ASIC version an optimized version of the AES module is available for FPGA implementations.
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