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SOurce Drain Architecture for Advanced MOS technology

Objective

The design, optimisation and fabrication of Accumulated Low Schottky Barrier MOSFETs on SOI is proposed in order to solve critical problems associated to the source/drain architecture and more specifically due to the specific contact resistance at the silicide/silicon interface. A complete validation of the ALSB SOI technology is proposed to move from a laboratory concept to an industrially attractive solution that meets requirements of the ITRS roadmap up to the 35 nm technology node. The design, optimisation and fabrication of Accumulated Low Schottky Barrier MOSFETs on SOI is proposed in order to solve critical problems associated to the source/drain architecture and more specifically due to the specific contact resistance at the silicide/silicon interface. A complete validation of the ALSB SOI technology is proposed to move from a laboratory concept to an industrially attractive solution that meets requirements of the ITRS roadmap up to the 35 nm technology node.

OBJECTIVES
The design, optimisation and fabrication of Accumulated Low Schottky Barrier MOSFETs on SOI is proposed in order to solve critical problems associated to the source/drain architecture and more specifically due to the specific contact resistance at the silicide/silicon interface. A complete validation of the ALSB SOI technology will be performed in order to move from a laboratory concept to an industrially attractive solution that meets requirements of the ITRS roadmap up to the 35 nm technology node. The objectives include the demonstration of improved performances of ALSB SOI MOSFETs over conventional architectures: immunity to short channel effects, suppressed sensitivity to dopant fluctuation, used of Schottky source/drain (S/D) contacts to suppress issues associated with tight control of S/D doping and reduced S/D specific contact resistance.

DESCRIPTION OF WORK
The relevant points to address in the SODAMOS project are:
- reproducibility of contacts with very low Schottky barrier to holes (PtGeSi showed promising Schottky barrier below 50 meV);
- obtention of very low Schottky barriers for electrons based on erbium alloys;
- demonstration of improved performances (high current, transconductance, high-frequency operation, best Ion/Ioff trade-off) of the ASBL-SOI technology over the conventional highly-doped source/drain architectures;
- electrical characterisation including both DC and microwave;
- process evaluation in industry.
Three technical workpackages have been set-up to achieve the work:
- material engineering: to study and elaborate low (ideally 0 eV) Schottky barrier contact on thin SOI films;
- device optimisation process/device simulations: to obtain the best design trade-off with respect to short channel effects and source/drain resistances;
- device fabrication and characterisation: to successively demonstrate three generations of ALSB-SOI MOSFETs corresponding to get length of 120 nm, 70 nm and ultimately in the 10-30 nm range;
- transfer and feasibility of Schottky barrier silicides and process in industrial environment.
1) Material engineering (WP1): a large collection of silicide materials and substrates was evaluated for providing a low Schottky barrier to hole. We have consolidated results obtained on Pt-based silicide through an exhaustive and original study including physical (XPS, TEM) and electrical characterization. Another very complete study on Ir silicide was also completed for publication. The work on Er-based silicide has significantly progressed. The capping layer strategy still needs to be consolidated in the perspective of actual integration in a MOSFET process. In report 2, we have shown that the SOI thinning process is now well established and holds the distinctive advantage to provide defect-free layers when compared to other techniques using thermal oxidation. During year 3 of the project, additional work on Schottky barrier extraction and characterization has been provided and supported by experimental work at the device level (i.e. with a strong connection to workpackage 3). Finally, TEM characterization of various stacks of thin material layers proved to be extremely useful to guarantee their integrity and uniformity. 2) Simulation (WP2): Over the first year, a significant progress was made in the assessment of the ALSB-SOI MOSFET architecture: major figures of merit such as threshold voltage roll-off, subthreshold swing, off-state current, max saturated current and transconductance have been carefully analyzed using the 'home-made' IMPACT3 2D device simulation code. A very original work on the modelling of the kinetic of growth of ultra thin oxides has also been proposed and consolidated by oxidation experiments. During year 3, additional work has been provided by ST Microelectronics to validate software updates introduced by the ISE TCAD company. It is worth noting that the simulation work was largely disseminated within different divisions of ST Microelectronics for other applications that involve Schottky junctions (e.g. bipolar transistor with Schottky buried collector, bulk acoustic wave resonators, low cost contact-less circuitry). 3) Device fabrication and characterization (WP3): During year 1, a major result was obtained using the gate overlap architecture, considering that a current level as high as 220 mA/mm was measured for a metallurgical channel length of 45.4 nm using PtSi-based S/D contacts. The results of this work are above state-of-the-art performance obtained on SOI or bulk. The SODAMOS project has significantly progressed in the development of elementary process steps with the demonstration of gate lengths patterning down to less than 20 nm. More specifically, investigations have mainly focused on the definition of the gate and spacers by dry etching and on the final silicidation step. A particular attention has been put on possible Pt bridging mechanisms over the encapsulated gate. XPS and TEM analysis were extensively used to rule out this scenario.

Detailed SEM and TEM characterizations of integrated p-type MOSFETs have validated the full SB-MOSFET process. At last, electrical characterizations have outlined excellent p-type MOSFETs performance. SODAMOS outputs have significantly improved the state-of-the-art with an on-state current above 300 microA/micron, up to 425 microA/micron and an off-state current still constrained in the sub-nA/micron. 4) Assessment of the silicide process in industrial environment (WP4) During year 2, the experimental work was performed on Pt-based germano-silicide systems. Sheet resistance and SEM investigations have been carried out for annealing temperatures ranging from 350 C and 550 C. During year 3, further analysis, XRD, XPS, TEM, AFM, and a kinetic study has been performed on these layers for further material characterization according to time, temperature, phases, and thickness parameters. It is recalled that the objective of ST Microelectronics was to evaluate of the ALSB-SOI MOSFET process, initially developed in academic laboratories. In that framework, it is clear that the most important work was to develop the elementary Pt-silicide building blocks at the material engineering level to ensure compatibility with current CMOS already running on process lines. From that standpoint, ST Microelectronics has capitalized work performed at IEMN and UCL to its own developments.

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CSC - Cost-sharing contracts

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CENTRE NATIONAL DE LA RECHERCHE SCIENTIFIQUE
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3, RUE MICHEL-ANGE
75794 PARIS CEDEX 16
France

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Last update: 13 June 2005

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Permalink: https://cordis.europa.eu/project/id/IST-2000-26475

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