REGATE Best Practice (first user) application experiment aims at the acquisition of advanced technology and tools as well as key knowledge and expertise in System-On-Chip ASIC microelectronics by the user partner. The target is to develop a SoC ASIC (ARM CPU, memory, peripheral modules) to upgrade an existing gateway product, enhancing its communication capabilities and reducing its cost. The proposer business sector is the development and marketing of advanced and high performance gateway systems for the residential and SOHO market. The user has systems design, PCB and certain FPGA expertise but no ASIC background. The acquisition of the proposed microelectronics technology will provide the user the capability to advance its practices, to design its own ASIC(s) for the gateways and extend its business to the fast evolving SOHO gateway market. The acquisition of the capability to design first time right SoC ASICs following a cost effective development cycle is of key importance.
DESCRIPTION OF WORK
REGATE will design and manufacture a high performance System-On-Chip ASIC component. The technical context as well as the main objectives of this project are: (1) The design, implementation, layout, timing verification, manufacturing and packaging of an advanced SoC ASIC targeting at the efficient performance of telecommunication functions while decreasing the cost of the target gateway system compared to off-the-self components solutions. (2) To reuse available peripheral modules for the ASIC, develop new ones (802.3 MAC, HDLC, DMA controller) and integrate them with an ARM IP core. (3) To develop an evaluation board and assess the developed SoC ASIC and microelectronics technology used. (4) To port available software and implement low level software functions for a comprehensive evaluation of the entire work, (5) To use VHDL compiler, synthesis and simulation tools and adoption of SoC ASIC microelectronics technology. The target of this ASIC is to integrate in one chip the core processing subsystem of an existing residential gateway so as to enhance performance and reduce cost.UMIST will contribute in the design, will perform the back-end design (physical layout), the post-layout timing verification, will investigate the packaging alternatives and train the proposer to these issues. The chip will be manufactured by UMC, a large ASIC manufacturer, using a 0.25um CMOS fabrication process. The choice of UMC is based on their support for Multi Project Wafer (MPW) runs, taking place every two months (or less), as well as on the fact that UMC already hold a licence for the proposed ARM core, thus highly reducing prototyping cost. The anticipated die size is about 50 mm2. In order to achieve the above main objectives, the project will place particular effort and emphasis on the tools to be used as well as on the appropriate training on them and the new technology. The Synopsys synthesizer and the Modelism simulator from Mentor will be acquired and adopted.
Funding SchemeDEM - Demonstration contracts