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Content archived on 2024-05-15

Verification of Microelectronics Systems Using Logic Compiler Technology


This project is a trial application of a new technology for Formal Verification of systems design, called Logic Compiler Technology, applicable both for hardware and software systems. The new technology is able to verify in a mathematical sense the correctness of a design according to its specification, thus reducing dramatically the time and the costs for system validation. The trial will focus on a safety critical microelectronics application development raising the key issues to be addressed during a typical formal verification process: the automatic elaboration of design and specification descriptions, the costs/benefits ratio including time-to-market, assessments of this design method by certification authorities. The expected positive result will help to promote the broader use of formal method in the area of microelectronics.

Work description:
WP1 Project management (CA, NSL, FZI, UoK, INRS)
WP2 Formal and informal specification phase (CA, FZI, UoK, INRS)Definition and formalisation of the system specification using both traditional and formal methods
WP3 Formal and informal design phase (UoK, CA, FZI, INRS)Design of hardware/software of the SIOD using both traditional and formal methods.
WP4 Comparative assessment and evaluation (INRS, CA,NSL, FZI, UoK)Verification using both traditional and formal verification methods derived from
WP3. It includes the cost/benefit analysis necessary to evaluate the technology with respect to their actual benefits.
WP5 Dissemination and exploitation (FZI, CA, NSL, UoK, INRS) Summarises the proposed actions for dissemination of the result of the project and use plan for the technology provider (NSL) and the end-user (CA)

End M4. Formal and informal specification phases: specification and costs analysis reports
End M7. Formal and informal design phases: design and costs analysis reports
End M11. Verification phases and comparative case study: verification and comparative assessment and evaluation reports
End M12. Dissemination report and use plan

Call for proposal

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EU contribution
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Total cost
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Participants (4)