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Integrated Design Methodology for enhANced Device Robustness

Objective

Due to the increasing scale of IC integration ("System on Chip") and growing demands for mobile applications, IC reliability against noise and high current pulses will be a major issue after 2002. The development of appropriate solutions in a sufficient time scale requires an efficient design methodology including fast, appropriate characterization and predictive device simulation. The project will develop an integrated methodology for the design of devices with enhanced robustness including a new two dimensional imaging system for internal parameters (non-invasive, real 2d imaging, 5 ns / 2 µm resolution) for fast device and circuit analysis during transient electrical stress, as well as improved device simulation, suitable for the occurring transient high temperatures. The simulation improvements will be implemented into commercial software and a feasibility study will establish the needs for an industrial system setup.

Objectives:
System miniaturization ("system on chip") and future applications will enormously increase the requirements for IC robustness against transient high engergetic electrical noise.

The main objectives of this project are:
- to develop a consistent methodology for designing robust devices,
- to define design rules and demonstrate examples of improved devices,
- to develop a new 2d optical characterization technique for internal parameters with <2µm spatial and 5ns temporal resolution,
- to evaluate the feasibility of the system for industrial use,
- to develop new electrical characterization techniques at high temperatures,
- to develop and calibrate physical models for device simulation in the temperature range above 700K under high current conditions and
- to implement the new models into a commercial device simulator.

Given this will be achieved, it can be envisaged that the robustness of such devices would be increased by a factor of 1.5 and the Time to Market of a typical smart power technology development shortened by about 5 months.

Work description:
The project is organized in 5 Work Packages (WP):
- Work Package 1: Design Methodology
-Work Package 2: Optical Characterization Development
- Work Package 3: High Temperature Physical Model Development
- Work Package 4: Project Management
- Work Package 5: Dissemination and Use

WP1 is dedicated to the conceptual frame of the project and to the realization of de-vice examples with enhanced robustness by means of the developed methodology. It starts with a task to update and further detail the User Requirements for the experimental setup and simulation software, proceeds with concepts, realization, simulation and experimental analysis of device examples and completes the methodology by specifying design rules and defining an optimised work flow.
WP2 will develop and calibrate the optical characterization system. It starts with calibration investigations by means of the existing predecessor method and continues consecutively building and calibrating a laboratory setup, studying the feasibility for industrial use and validating the performance of the system.
WP3 aims at extending the present device simulation capabilities towards higher operating temperatures and transient high current stress. It starts with the development of new electrical characterization strategies and suitable test structures, parallel to the evaluation of existing models in the temperature range above 700K. Optical and electrical characterization of the test structures, together with the corresponding device simulations and dedicated theoretical work will lead to the development and calibration of new physical models for the device simulation. The developed new models will be implemented into a commercial device simulator.
WP4 manages the project. It covers coordination, control and corrective actions for the project, as well as the contact to the Commission and the preparation of the Pro-gress Reports.
WP5 secures the Dissemination and Use of the results gained during the project. It prepares the Dissemination and Use Plan and the Technology Implementation Plan, coordinates the use-related activities of WPs 1 through 3 and disseminates directly by publications and patents.

Milestones:
- Characterization setup technical specifications (Month 3)
- Model deficiencies identified (Month 6)
- Testchip design (Month 4, Month 18)
- Laboratory 2d optical setup working (Month 9)
- Characterization Methods for parameter extraction at high temperatures (Month 24)
- Optical technique calibrated and meeting specifications (Month 21)
- Demonstration of devices with enhanced robustness (Month 28)
- New simulation models calibrated (Month 36)

Funding Scheme

CSC - Cost-sharing contracts
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Coordinator

INFINEON TECHNOLOGIES AG
Address
St. Martin Strasse 53
81609 Muenchen
Germany

Participants (4)

ALMA MATER STUDIORUM - UNIVERSITA DI BOLOGNA
Italy
Address
Via Zamboni 33
40126 Bologna
EIDGENOESSISCHE TECHNISCHE HOCHSCHULE ZUERICH
Switzerland
Address
Raemistrasse 101
8092 Zuerich
ISE INTEGRATED SYSTEMS ENGINEERING AG
Switzerland
Address
Affolternstrasse 52
8050 Zuerich
TECHNISCHE UNIVERSITAET WIEN - INSTITUT FUER FESTKOERPERELEKTRONIK
Austria
Address
Floragasse 7
1040 Wien