Objective
The objective of PUSSEE is to introduce the formal proof of system properties throughout a modular system design methodology that integrates sub-systems co-verification with system refinement and reusability of virtual system components. This will be done by combining the UML and B languages to allow the verification of system specifications through the composition of proven sub-systems (in particular interfaces, using the VSIA/SLIF standard). The link of B with C, VHDL and System C will extend the correct-by-construction design process to lower system-on-chip (SoC) development stages. Prototype tools will be developed for the code generation from UML and B, and existing B verification tools will be extended to support IP reuse, according to the VSI Alliance work. The methodology and tools will be validated through the development of three industrial applications: a wireless mobile terminal, an IP encryptor for secure data transmission through internet and a network management module for automobiles.
Work description:
To satisfy a need for products of high reliability with short time-to-market, PUSSEE introduces two key aspects, reusability and formal proof of system properties.
Reusability, although popular in the software world, is not yet usual in the domain of embedded systems because few design methods can integrate reusable sub-systems. The PUSSEE approach allows the reuse of existing components at various levels of the design. UML system specifications provide reusable system models through concepts like inheritance. Then virtual components, as defined in VSI Alliance, address reusability during later development stages.
The second important innovation introduced by PUSSEE, is the use of the B language for proving the properties of embedded system on chips (SoC). The formality of B complements the lack of formal semantics, which is the major drawback of UML. The two languages, jointly used to develop complex systems formally proven from the earliest design stage, allow to discover mistakes, inconsistencies or inefficiencies early enough to be fixed at minimum cost. Moreover, the reusability of B abstract machines at any level of refinement, with preservation of the integrity of the proven system specification, introduces a breakthrough in the reusability practice and paves the way to interface based design "a la" VSIA/SLIF. A set of tools enabling a seamless use of the two languages will support the approach.
PUSSEE goals can be summarized as follows:
- Interface base design allowing sub-systems composition;
- Definition of a synergy between UML and B
- Tool support throughout all stages of the system specifications refinement;
- Elaboration of reusable components for both system specification (reusable UML and B models) and system development (reusable virtual components).
The selected applications from the automotive and telecommunication domains will materialize the expectations of the participating system companies whose role is:
- Transferring the know-how and current trends from two highly demanding design domains;
- Learning the use of formal languages required for proven and reliable system development;
- Contributing to integrate in the PUSSEE methodology their actual needs very accurately;
- Assessing the applicability of this methodology through real industry cases.
The PUSSEE research activities will be guided and constrained by their actual needs.
Milestones:
- A tool linking Rational Rose to Atelier-B by providing translations between UML diagrams and B;
- A prototype tool that translates B to system-C and VHDL;
- A study of how the B method can be complemented to better support specification, refinement and code generation of systems with real-time properties;
- A method with tool support for interface based design (VSIA/SLIF) and integration of legacy components;
- User guidelines and methodology assessment reports from industrial use cases.
Results will be commercialised and disseminated through conferences, courses and web pages.
Fields of science (EuroSciVoc)
CORDIS classifies projects with EuroSciVoc, a multilingual taxonomy of fields of science, through a semi-automatic process based on NLP techniques.
CORDIS classifies projects with EuroSciVoc, a multilingual taxonomy of fields of science, through a semi-automatic process based on NLP techniques.
- natural sciencescomputer and information sciencesinternet
- natural sciencescomputer and information sciencessoftwaresoftware applicationssimulation software
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Topic(s)
Call for proposal
Data not availableFunding Scheme
CSC - Cost-sharing contractsCoordinator
405 08 GOETEBORG
Sweden